C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 65

• Manufacturer Part Number: C8051F530-TB
• Description: BOARD PROTOTYPE W/C8051F530
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F530-TB

• Contents: Board
• Processor To Be Evaluated: C8051F52xA and C8051F53xA
• Interface Type: USB
• Lead Free Status / RoHS Status: Vendor undefined / Vendor undefined
• For Use With/related Products: C8051F530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SFR Definition 4.5. ADC0CF: ADC0 Configuration
Note: Round the result up.
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
Bits2–1: AD0RPT1–0: ADC0 Repeat Count.
Bit0:
R/W
Bit7
SAR Conversion clock is derived from FCLK by the following equation, where AD0SC refers
to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock requirements are given in
Table 2.3 on page 29.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is the Burst Mode Oscillator, specified in Table 2.3.
Controls the number of conversions taken and accumulated between ADC0 End of
Conversion (ADCINT) and ADC0 Window Comparator (ADCWINT) interrupts. A convert
start is required for each conversion unless Burst Mode is enabled. In Burst Mode, a single
convert start can initiate multiple self-timed conversions. Results in both modes are
accumulated in the ADC0H:ADC0L register. When AD0RPT1–0 are set to a value other
than '00', the AD0LJST bit in the ADC0CN register must be set to '0' (right justified).
00: 1 conversion is performed.
01: 4 conversions are performed and accumulated.
10: 8 conversions are performed and accumulated.
11: 16 conversions are performed and accumulated.
GAINEN: Gain Enable Bit.
Controls the gain programming. For more information of the usage, refer to the following
chapter: Section “4.4. Selectable Gain” on page 60.
AD0SC
R/W
Bit6
=
------------------- - 1
CLK
AD0SC
FCLK
R/W
Bit5
SAR
–
*
R/W
Bit4
C8051F52x/F52xA/F53x/F53xA
or
Rev. 1.3
R/W
Bit3
CLK
SAR
R/W
Bit2
=
AD0RPT
----------------------------
AD0SC
FCLK
R/W
Bit1
+
1
GAINEN
R/W
Bit0
SFR Address:
Reset Value
11111000
0xBC
65