C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 185

• Manufacturer Part Number: C8051F530-TB
• Description: BOARD PROTOTYPE W/C8051F530
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F530-TB

• Contents: Board
• Processor To Be Evaluated: C8051F52xA and C8051F53xA
• Interface Type: USB
• Lead Free Status / RoHS Status: Vendor undefined / Vendor undefined
• For Use With/related Products: C8051F530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SFR Definition 18.1. TCON: Timer Control
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF1
R/W
Bit7
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 1 service routine if IT1 = 1. When IT1 = 0, this flag is set to 1 when INT0 is active as
defined by bit IN1PL in register IT01CF (see SFR Definition 10.5. “IT01CF: INT0/INT1 Con-
figuration” on page 105).
IT1: Interrupt 1 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive. INT0 is
configured active low or high by the IN1PL bit in the IT01CF register (see SFR
Definition 10.5. “IT01CF: INT0/INT1 Configuration” on page 105).
0: INT0 is level triggered.
1: INT0 is edge triggered.
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 0 service routine if IT0 = 1. When IT0 = 0, this flag is set to 1 when INT0 is active as
defined by bit IN0PL in register IT01CF (see SFR Definition 10.5. “IT01CF: INT0/INT1 Con-
figuration” on page 105).
IT0: Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive. INT0 is
configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition 10.5.
“IT01CF: INT0/INT1 Configuration” on page 105).
0: INT0 is level triggered.
1: INT0 is edge triggered.
TR1
R/W
Bit6
TF0
R/W
Bit5
TR0
R/W
Bit4
C8051F52x/F52xA/F53x/F53xA
Rev. 1.3
R/W
IE1
Bit3
R/W
IT1
Bit2
R/W
IE0
Bit1
SFR Address:
R/W
IT0
Bit0
Addressable
Reset Value
00000000
0x88
Bit
185