C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 126

• Manufacturer Part Number: C8051F530-TB
• Description: BOARD PROTOTYPE W/C8051F530
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F530-TB

• Contents: Board
• Processor To Be Evaluated: C8051F52xA and C8051F53xA
• Interface Type: USB
• Lead Free Status / RoHS Status: Vendor undefined / Vendor undefined
• For Use With/related Products: C8051F530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F52x/F52xA/F53x/F53xA
SFR Definition 13.1. XBR0: Port I/O Crossbar Register 0
126
Note: Refer to Section “20. Device Specific Behavior” on page 209.
Bit7–6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
Bit7
-
RESERVED. Read = 00b; Must write 00b.
CP0AE: Comparator0 Asynchronous Output Enable
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
CP0E: Comparator0 Output Enable
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
SYSCKE: /SYSCLK Output Enable
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK output routed to Port pin.
LINE. Lin Output Enable
SPI0E: SPI I/O Enable
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO pins.
URT0E: UART I/O Output Enable
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins (P0.3 and P0.4) or (P0.4 and P0.5).*
R/W
Bit6
-
CP0AE
R/W
Bit5
CP0E
R/W
Bit4
SYSCKE
Rev. 1.3
R/W
Bit3
LINE
R/W
Bit2
SPI0E
R/W
Bit1
SFR Address:
URT0E
R/W
Bit0
00000000
Reset Value
0xE1