MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet
MC-78F0712-KIT
Specifications of MC-78F0712-KIT
Related parts for MC-78F0712-KIT
MC-78F0712-KIT Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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User’s Manual PD78F0711, 78F0712 8-Bit Single-Chip Microcontrollers PD78F0711 PD78F0712 Document No. U17890EJ2V0UD00 (2nd edition) Date Published October 2007 NS © 2006 Printed in Japan ...
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User’s Manual U17890EJ2V0UD ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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EEPROM, IECUBE, and MINICUBE are registered trademarks of NEC Electronics Corporation in japan and Germany. Windows, Windows NT, and Windows XP are registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/ trademark ...
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Readers This manual is intended for user engineers who wish to understand the functions of the PD78F0711, 78F0712 and design and develop application systems and programs for this device. The target product is as follows. PD78F0711, 78F0712 Purpose This manual ...
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices PD78F0711, 78F0712 User’s Manual 78K/0 Series Instructions User’s Manual Documents Related to Development Tools (Software) ...
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CHAPTER 1 OUTLINE ............................................................................................................................ 14 1.1 Features..................................................................................................................................... 15 1.2 Applications .............................................................................................................................. 16 1.3 Ordering Information................................................................................................................ 16 1.4 Pin Configuration (Top View) .................................................................................................. 17 1.5 Block Diagram........................................................................................................................... 18 1.6 Outline of Functions................................................................................................................. 19 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 21 2.1 Pin ...
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Direct addressing ......................................................................................................................... 49 3.4.4 Short direct addressing ................................................................................................................ 50 3.4.5 Special function register (SFR) addressing .................................................................................. 51 3.4.6 Register indirect addressing ......................................................................................................... 52 3.4.7 Based addressing......................................................................................................................... 53 3.4.8 Based indexed addressing ........................................................................................................... 54 3.4.9 Stack addressing.......................................................................................................................... 55 CHAPTER ...
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Registers Controlling 10-Bit Inverter Control Timer ........................................................... 102 6.5 Registers Controlling 10-Bit Inverter Control Timer ........................................................... 107 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00........................................................................... 114 7.1 Functions of 16-Bit Timer/Event Counter 00 ....................................................................... 114 7.2 Configuration of 16-Bit Timer/Event Counter ...
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Registers Controlling Real-Time Output Port ...................................................................... 183 10.4 Operation of Real-Time Output Port ..................................................................................... 187 10.5 Using Real-Time Output Port................................................................................................. 192 10.6 Notes on Real-Time Output Port ........................................................................................... 193 CHAPTER 11 DC INVERTER CONTROL FUNCTION ......................................................................... 194 CHAPTER 12 ...
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CHAPTER 16 INTERRUPT FUNCTIONS ............................................................................................ 256 16.1 Interrupt Function Types ....................................................................................................... 256 16.2 Interrupt Sources and Configuration.................................................................................... 256 16.3 Registers Controlling Interrupt Functions ........................................................................... 260 16.4 Interrupt Servicing Operations.............................................................................................. 268 16.4.1 Maskable interrupt request acknowledgement ............................................................................268 16.4.2 Software interrupt request ...
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Processing of Pins on Board................................................................................................. 315 22.5.1 FLMD0 pin.................................................................................................................................. 315 22.5.2 FLMD1 pin.................................................................................................................................. 315 22.5.3 Serial interface pins.................................................................................................................... 316 22.5.4 RESET pin.................................................................................................................................. 318 22.5.5 Port pins ..................................................................................................................................... 318 22.5.6 Other signal pins ........................................................................................................................ 318 22.5.7 Power supply.............................................................................................................................. 318 22.6 ...
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A.5 Debugging Tools (Hardware) ................................................................................................ 364 A.5.1 When using in-circuit emulator QB-780714....................................................................................364 A.5.2 When using on-chip debug emulator QB-78K0MINI.......................................................................364 A.5.3 When using on-chip debug emulator with programming function QB-MINI2 ..................................365 A.6 Debugging Tools (Software).................................................................................................. 365 APPENDIX B REGISTER INDEX......................................................................................................... 366 ...
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The PD78F0711 and 78F0712 are 8-bit single-chip microcontrollers which use a 78K/0 CPU core and incorporate <R> peripheral functions, such as ROM/RAM, a timer/counter, a serial interface, an A/D converter, and a watchdog timer. The PD78F0711 and 78F0712 are products ...
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Features Minimum instruction execution time can be changed from high speed (0 MHz operation with) X1 input clock) to low-speed (8. 240 kHz operation with internal low-speed oscillation clock) On-chip internal high-speed oscillator (8 ...
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... Industrial equipment Pumps control ,etc. 1.3 Ordering Information Part Number PD78F0712MC-5A4-A 30-pin plastic SSOP (7.62 mm (300)) PD78F0711MC-5A4-A 30-pin plastic SSOP (7.62 mm (300)) Remark Products with -A at the end of the part number are lead-free products. 16 CHAPTER 1 OUTLINE Package User’s Manual U17890EJ2V0UD ...
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Pin Configuration (Top View) 30-pin plastic SSOP (7.62 mm (300)) ANI1/P21 ANI0/P20 TW0TO5/RTP15 TW0TO4/RTP14 TW0TO3/RTP13 RESET FLMD0 TW0TO2/RTP12 TW0TO1/RTP11 TW0TO0/RTP10 Caution Connect the AV pin Pin Identification ADTRG: ...
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Block Diagram TW0TO0 to TW0TO5 6 10-bit INVERTER CONTROL TIMER TW0TOFFP/P00 TW0 TO00/TI001/P54 16-bit TIMER/ EVENT COUNTER 00 TI000/P53 8-bit TIMER/ TI50/TO50/P50 EVENT COUNTER 50 8-bit TIMER/ EVENT COUNTER 51 WATCHDOG TIMER REAL-TIME 6 RTP10 to RTP15 OUTPUT PORT ...
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Outline of Functions Item Internal Flash memory (self- memory programming supported) High-speed RAM Memory space X1 input clock (oscillation frequency) Internal high-speed oscillation clock Internal low-speed oscillation clock General-purpose registers Minimum instruction execution time Instruction set I/O ports Timers ...
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An outline of the timer is shown below. Operation mode Interval timer External event counter Function Timer output PPG output PWM output Pulse width measurement Square-wave output Watchdog timer Interrupt source 20 CHAPTER 1 OUTLINE 10-Bit Inverter 16-Bit Timer/ Control ...
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Pin Function List There are two types of pin I/O buffer power supplies: AV supplies and the pins is shown below. <R> (1) Port pins Pin Name I/O P00 I/O P01 P02 P03 P13 I/O P14 P16 P17 P20 ...
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Non-port pins Pin Name I/O INTP0 Input External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be INTP1 specified INTP2 INTP3 INTP5 RxD00 Input Serial data input to ...
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Description of Pin Functions 2.2.1 P00 to P03 (port 0) P00 to P03 function as a 4-bit I/O port. These pins also function as external interrupt request input, timer output stop external signal, and A/D converter trigger input. The ...
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P20 to P23 (port 2) P20 to P23 function as an 4-bit input-only port. These pins also function as pins for A/D converter analog input. The following operation modes can be specified in 1-bit units. (1) Port mode P20 ...
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AV REF This is the A/D converter reference voltage input pin. When the A/D converter is not used, connect this pin directly to V Note Connect port 2 directly to V 2.2 This is the A/D converter ...
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Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. See Figure 2-1 for the configuration of the I/O circuit of each type. Pin ...
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Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 4-B Data Output disable Type 5-H Pullup enable V DD Data P-ch Output N-ch disable Input enable CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List Type 8-C Pullup enable ...
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Memory Space PD78F0711 and 78F0712 products can each access memory space. Figures 3-1 and 3-2 show the memory map. Caution Because the initial value of the memory size switching register (IMS) is CFH, set IMS to ...
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Figure 3-2. Memory Map ( PD78F0712) FFFFH Special function registers 256 FF00H FEFFH General-purpose registers 32 FEE0H FEDFH Internal high-speed RAM 768 FC00H FBFFH Data memory space Reserved 4000H 3FFFH Flash memory 16384 0084H 0083H 0000H Notes 1. This area ...
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Internal program memory space The internal program memory space stores the program and table data. Normally addressed with the program counter (PC). PD78F0711 and 78F0712 products incorporate internal ROM (flash memory), as shown below. Part Number PD78F0711 ...
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CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 3.1.2 Internal data memory space PD78F0711 and 78F0712 products incorporate the following RAMs. (1) Internal high-speed RAM The ...
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Figure 3-3. Correspondence Between Data Memory and Addressing ( PD78F0711) FFFFH Special function registers (SFR) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 768 8 bits FE20H FE1FH Note 1 FC00H ...
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Figure 3-4. Correspondence Between Data Memory and Addressing ( PD78F0712) FFFFH Special function registers (SFR) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 768 8 bits FE20H FE1FH Note 1 FC00H ...
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Processor Registers The PD78F0711 and 78F0712 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word ...
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Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. (d) ...
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Figure 3-8. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H (b) CALL, CALLF, CALLT instructions (when SP = FEE0H (c) Interrupt, BRK instructions (when SP = FEE0H ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H SP FEDFH FEDEH SP FEDEH (b) RET instruction (when SP = FEDEH) FEE0H FEE0H SP FEDFH FEDEH ...
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General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers ( and H). ...
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Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit ...
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... TMC50 R/W PU0 R/W PU1 R/W PU5 R/W DCCTL01 R/W DSCTL02 R/W TM51 R CR51 R/W TCL51 R/W TMC51 R/W EGP R/W EGN R/W User’s Manual U17890EJ2V0UD Manipulatable Bit Unit After Reset 8 Bits 16 Bits 00H 00H Undefined 00H 0000H 0000H 0000H ...
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Table 3-3. Special Function Register List (2/4) Address Special Function Register (SFR) Name FF50H 10-bit buffer register 4 FF51H FF52H 10-bit buffer register 5 FF53H FF54H 10-bit compare register 0 FF55H FF56H 10-bit compare register 1 FF57H FF58H 10-bit compare ...
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... MOC R/W OSTC R OSTS R/W RESF R RTBL01 R/W RTBH01 R/W RTPM01 R/W RTPC01 R/W PFCMD W PFS R/W FLPMC R/W IF0 IF0L R/W IF0H R/W IF1 IF1L R/W IF1H R/W MK0 MK0L R/W MK0H R/W MK1 MK1L R/W MK1H R/W PR0 PR0L ...
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Address Special Function Register (SFR) Name FFF0H Internal memory size switching register FFFBH Processor clock control register <R> FFFDH System wait control register Note Because the initial value of the internal memory size switching register (IMS) is CFH, set IMS ...
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Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and ...
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Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits the immediate data of an operation code are transferred to the program counter (PC) and branched. ...
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Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers ...
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Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn operation code. Register addressing is carried ...
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Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code [Illustration] 7 CHAPTER ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function ...
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Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the ...
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Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing ...
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Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and ...
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Based indexed addressing [Function] The register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank ...
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Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation ...
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Port Functions There are two types of pin I/O buffer power supplies: AV supplies and the pins is shown below. <R> products are provided with the ports shown in Figure 4-1, which enable variety of control PD78F0711 and 78F0712 ...
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Pin Name I/O P00 I/O Port 0. 4-bit I/O port. P01 Input/output can be specified in 1-bit units. P02 Use of an on-chip pull-up resistor can be specified by a P03 software setting. P13 I/O Port 1. 4-bit I/O port. ...
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Port Configuration Ports consist of the following hardware. Item Control registers Port mode register (PM0, PM1, PM5) Port register (P0, P1, P2, P5) Pull-up resistor option register (PU0, PU1, PU5) Port Total: 15 (CMOS I/O: 11, CMOS input: 4) ...
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Port 1 Port 4-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P13, P14, P16, ...
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WR PU PU1 PU14 RD WR PORT Output latch (P14 PM1 PM14 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR××: Write signal 60 CHAPTER 4 PORT FUNCTIONS Figure 4-4. ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P16 WR PU PU1 PU16 RD WR PORT Output latch (P16 PM1 PM16 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR××: Write ...
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WR PU PU1 PU17 Alternate function RD WR PORT Output latch (P17 PM1 PM17 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR××: Write signal 62 CHAPTER 4 PORT FUNCTIONS Figure 4-6. ...
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Port 2 Port 4-bit input-only port. This port can also be used for A/D converter analog input. Figure 4-7 shows a block diagram of port 2. RD A/D converter RD: Read signal <R> Caution Connect AV ...
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Port 5 Port 3-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P53 WR PU PU5 PU53 Alternate function RD WR PORT Output latch (P53 PM5 PM53 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 RD: Read signal ...
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Registers Controlling Port Function Port functions are controlled by the following three types of registers. Port mode registers (PM0, PM1, PM5) Port registers (P0, P1, P2, P5) Pull-up resistor option registers (PU0, PU1, PU5) (1) Port mode registers (PM0, ...
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Table 4-4. Settings of Port Mode Register and Output Latch When Using Alternate Function Pin Name Function Name P00 INTP0 TW0TOFFP P01 INTP1 P02 INTP2 P03 INTP3 ADTRG P13 RxD00 P14 TxD00 P17 FLMD1 P20-P23 ANI0-ANI3 P50 TI50 TO50 P53 ...
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Port registers (P0, P1, P2, P5) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If ...
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Pull-up resistor option registers (PU0, PU1, and PU5) These registers specify whether the on-chip pull-up resistors of P00 to P03, P13, P14, P16, P17, P50, P53, P54 are to be used or not. On-chip pull-up resistors can be used ...
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Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed ...
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Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) <R> When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not ...
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Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following kind of system clock and clock oscillator are selectable. (1) High-speed system clock <1> X1 oscillator This circuit ...
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... Table 5-1. Configuration of Clock Generator Configuration Processor clock control register (PCC) Internal oscillation mode register (RCM) Main OSC control register (MOC) Main clock mode register (MCM) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) System wait control register (VSWC) X1 oscillator ...
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... XH Controller Option byte 1: Internal high-speed oscillation clock 0: X1 clock RSTOP Intrenal oscillation mode register (RCM) Internal bus Main clock Processor clock mode register control register (MCM) (PCC) PCC2 PCC1 PCC0 MCS MCM0 3 f Main system XP Prescaler clock switch ...
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... The following seven registers are used to control the clock generator. Processor clock control register (PCC) Internal oscillation mode register (RCM) Main OSC control register (MOC) Main clock mode register (MCM) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) <R> ...
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... XP Notes 1. The main clock mode register (MCM) is used to set the main system clock supplied to CPU clock (high-speed system clock or internal low-speed oscillation clock) (see Figure 5-5). 2. The option byte is used to select the high-speed system clock (X1 clock or internal high-speed oscillation clock). 3. Setting prohibited. ...
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... Internal low-speed oscillator stopped Note Bit are read-only. Caution When setting RSTOP sure to confirm that the CPU operates with the high- speed system clock (when MCS = 1). In addition, stop peripheral hardware that is operating on the internal low-speed oscillation clock before setting RSTOP to 1. ...
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... Oscillator stopped Cautions 1. When setting MSTOP sure to confirm that the CPU operates with the internal low-speed oscillation clock (When MCS = 0). In addition, stop peripheral hardware that is operating on the high-speed system clock before setting MSTOP The peripheral hardware cannot operate if the high-speed system clock is stopped when the high-speed system clock is selected as the peripheral hardware clock ...
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... This register selects the main system clock (f The main system clock becomes a source clock to the CPU and the peripheral hardware. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 5-5. Format of Main Clock Mode Register (MCM) ...
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Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal low-speed oscillation clock used as the CPU ...
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Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for ...
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System wait control register (VSWC) <R> This register is used to control wait states when a high-speed CPU and a low-speed peripheral I/O are connected. VSWC can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input ...
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System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (Standard: 20 MHz) connected to the X1 and X2 pins. Oscillation can be controlled by the main OSC control register (MOC). An ...
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Examples of Incorrect Resonator Connection Figure 5-10 shows examples of incorrect resonator connection. Figure 5-10. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (c) Wiring near high alternating current CHAPTER ...
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Figure 5-10. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched 5.4.3 Internal high-speed oscillator Internal high-speed oscillator is incorporated in the PD78F0711 and 78F0712. Oscillation can be controlled by the main OSC control register (MOC). ...
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Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 5-1). Main system clock f XP High-speed system clock clock f X ...
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Figure 5-11. Timing Diagram of CPU Default Start Using Internal Low-speed Oscillator (a) When X1 clock is selected as high-speed system clock X1 clock ( Internal low-speed clock ( RESET CPU clock Operation stopped: 17/f RL ...
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... When the RESET signal is generated, bit 0 of the main clock mode register (MCM) is cleared to 0 and the internal low-speed oscillation clock is set as the CPU clock. However, a clock is supplied to the CPU after 17 clocks of the internal low-speed oscillation clock have elapsed after RESET release (or clock supply to the CPU stops for 17 clocks) ...
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... Interrupt STOP instruction Notes 1. When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register (MCM the case of the X1 clock, check the oscillation stabilization time status using the oscillation stabilization time counter status register (OSTC) before shifting from status 2 to status 3 after reset and STOP are released ...
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... STOP are released. In the case of the internal high-speed oscillation clock, secure wait time (350 s) by software. 2. When shifting from status 2 to status 1, make sure that MCS The watchdog timer operates using internal low-speed oscillation clock even in STOP mode if “Internal low-speed oscillator cannot be stopped” is selected by an option byte. Internal low-speed oscillation clock division can be selected as the count source of 8-bit timer 51 (TM51), so clear the watchdog timer using the TM51 interrupt request before watchdog timer overflow ...
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... Remark MSTOP: Bit 7 of the main OSC control register (MOC) RSTOP: Bit 0 of the internal oscillation mode register (RCM) MCM0: Bit 0 of the main clock mode register (MCM) Table 5-4. Oscillation Control Flags and Clock Oscillation Status MSTOP = 1 RSTOP = 0 ...
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... Time Required to Switch Between Internal Low-speed Oscillation Clock and High-speed System Clock Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the internal low-speed oscillation clock and high-speed system clock. In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions are executed using the pre-switch clock after switching MCM0 (see Table 5-5) ...
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Time Required for CPU Clock Switchover The CPU clock can be switched using bits (PCC0 to PCC2) of the processor clock control register (PCC). The actual switchover operation is not performed immediately after rewriting to the ...
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... Oscillation stabilization time status register OSTC = 00H Note ; Oscillation stabilization time f OSTS = 05H Each processing Note ; X1 clock oscillation stabilization time status check OSTC check X1 clock oscillation stabilization time has elapsed PCC setting MCM0 1 MCM.1 (MCS) is changed from High-speed system clock operation User’s Manual U17890EJ2V0UD ...
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... Oscillation stabilization time status register OSTC = 00H Each processing Oscillation stabilization time wait of the internal high-speed oscillator (NOP processing) PCC setting MCM0 1 High-speed system clock operation User’s Manual U17890EJ2V0UD = f CPU Internal low-speed oscillation clock (@ f = 480 kHz(max.)) RL : 168 clock 168/0.48 = 350 s MCM.1 (MCS) is changed from ...
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... Note Required only when “Can be stopped by software” is selected for internal low-speed oscillator by an option byte. 96 CHAPTER 5 CLOCK GENERATOR MCM = 03H ; High-speed system clock operation Note RCM.0 (RSTOP No: RSTOP = 0 MCM0 0 Internal low-speed oscillation clock operation User’s Manual U17890EJ2V0UD ; Internal low-speed oscillator stopped? ; Internal low-speed oscillation clock operation MCM.1 (MCS) is changed from ...
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... CHAPTER 5 CLOCK GENERATOR Table 5-7. Clock and Register Setting Setting Flag MCM Register MOC Register MCM0 MSTOP User’s Manual U17890EJ2V0UD Status Flag RCM Register MCM Register Note 1 RSTOP MCS ...
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CHAPTER 6 10-BIT INVERTER CONTROL TIMER 6.1 Outline of 10-Bit Inverter Control Timer The 10-bit inverter control timer makes inverter control possible. It consists of an 8-bit dead-time generation timer, and allows non-overlapping active-level output. 6.2 Function of 10-Bit Inverter ...
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Inverter timer control register (TW0C) CE0 TCL02 TCL01 TCL00 TW0UDC TW0BFCM3 TW0CM3 <R> TW0BFCM0 TW0CM0 TW0BFCM1 TW0CM1 TW0BFCM2 TW0CM2 ...
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CHAPTER 6 10-BIT INVERTER CONTROL TIMER (1) 10-bit up/down counter (TW0UDC) TW0UDC is a 10-bit up/down counter that counts count pulses in synchronization with the rising edge of the count clock. When the timer starts, the number of count pulse ...
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CHAPTER 6 10-BIT INVERTER CONTROL TIMER (5) 10-bit buffer registers (TW0BFCM0 to TW0BFCM5) TW0BFCM0 to TW0BFCM5 are 10-bit registers. They transfer data to the compare register (TW0CM0 to TW0CM5) corresponding to each buffer register at the timing ...
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CHAPTER 6 10-BIT INVERTER CONTROL TIMER 6.4 Registers Controlling 10-Bit Inverter Control Timer The following four registers control the 10-bit inverter control timer. Inverter timer control register (TW0C) Inverter timer mode register (TW0M) A/D trigger selection register (TW0TRGS) Inverter timer ...
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CHAPTER 6 10-BIT INVERTER CONTROL TIMER Figure 6-2. Format of Inverter Timer Control Register Address: FF88H After reset: 00H Symbol <7> 6 TW0C CE0 0 CE0 0 Clear and stop (TW0TO0 to TW0TO5 are Hi-Z) 1 Count enable TCL02 TCL01 ...
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CHAPTER 6 10-BIT INVERTER CONTROL TIMER (2) Inverter timer mode register (TW0M) TW0M controls the operation of and specifies the active level of the TW0TO0 to TW0TO5 outputs. TW0M is set by a 1-bit or 8-bit memory manipulation instruction. RESET ...
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CHAPTER 6 10-BIT INVERTER CONTROL TIMER Remarks 1. TW0TO0 to TW0TO5 become Hi-Z state in the following cases. However, the TW0UDC, DTM0 to DTM2, and RTM0 timers do not stop if CE0 = 1 is set. A valid edge is ...
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A/D trigger selection register (TW0TRGS) TW0TRGS is a register used to select the A/D converter trigger signal from INTTW0CM4 and INTTW0CM5, which are generated upon a match between the compare register (TW0CM4, TW0CM5) and timer counter (TW0UDC). TW0TRGS can ...
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CHAPTER 6 10-BIT INVERTER CONTROL TIMER 6.5 Registers Controlling 10-Bit Inverter Control Timer (1) Setting procedure (a) The TW0UDC count clock is set with the TCL00 to TCL02 bits of inverter timer control register (TW0C) and the occurrence frequency of ...
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CHAPTER 6 10-BIT INVERTER CONTROL TIMER (2) Output waveform widths corresponding to set values PWM = TW0CM3 2 T cycle TW0 Dead-time width = T = (TW0DTIME + 1) DTM Active width of positive phase (TW0TO0, TW0TO2, TW0TO4 pin) = ...
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CHAPTER 6 10-BIT INVERTER CONTROL TIMER (3) Operation timing Figure 6-6. TW0UDC Operation Timing (Basic Operation) TW0UDC a 0 TW0BFCMn TW0CMn TW0BFCM3 TW0CM3 F/F DTMn TW0TO0, TW0TO2, TW0TO4 TW0TO1, TW0TO3, TW0TO5 t Remarks ...
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CHAPTER 6 10-BIT INVERTER CONTROL TIMER Figure 6-7. TW0UDC Operation Timing (TW0CMn (TW0BFCMn) ≥ TW0CM3 (TW0BFCM3)) TW0UDC a 0 TW0BFCMn TW0CMn TW0BFCM3 TW0CM3 F/F DTMn TW0TO0, TW0TO2, TW0TO4 TW0TO1, TW0TO3, TW0TO5 t Remarks ...
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Figure 6-8. TW0UDC Operation Timing (TW0CMn (TW0BFCMn) = 000H) X TW0UDC a 0 TW0BFCMn b a TW0CMn Y TW0BFCM3 X TW0CM3 F/F DTMn TW0TO0, TW0TO2, TW0TO4 TW0TO1, TW0TO3, TW0TO5 t Remarks Dead ...
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Figure 6-9. TW0UDC Operation Timing (TW0CMn (TW0BFCMn) = TW0CM3 – 1/2DTM, TW0CMn (TW0BFCMn) > TW0CM3 – 1/2DTM) TW0UDC 0 TW0BFCMn – —DTM) TW0CMn 2 TW0BFCM3 TW0CM3 F/F DTMn TW0TO0, TW0TO2, TW0TO4 TW0TO1, TW0TO3, TW0TO5 Remarks 1. ...
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CHAPTER 6 10-BIT INVERTER CONTROL TIMER Figure 6-10. TW0UDC Operation Timing (IDEV02 to IDEV00 = 000B, TW0TRGS = 03H TW0UD TW0BFCM4 TW0CM4 TW0BFCM5 TW0CM5 TW0BFCM3 TW0CM3 INTTW0CM3 INTTW0CM4 INTTW0CM5 INTTW0ADTR ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.1 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. Interval timer PPG output Pulse width measurement External event counter Square-wave output One-shot pulse output (1) Interval timer 16-bit ...
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... Configuration 16 bits (TM00) 16-bit timer capture/compare register: 16 bits (CR00, CR01) TI000, TI001 TO00, output controller 16-bit timer mode control register 00 (TMC00) 16-bit timer capture/compare control register 00 (CRC00) 16-bit timer output control register 00 (TOC00) Prescaler mode register 00 (PRM00) Port mode register 5 (PM5) ...
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... TM00 The count value is reset to 0000H in the following cases. <1> At RESET input <2> If TMC003 and TMC002 are cleared <3> If the valid edge of the TI000 pin is input in the mode in which clear & start occurs upon input of the valid edge of the TI000 pin < ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Table 7-2. CR00 Capture Trigger and Valid Edges of TI000 and TI001 Pins (1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1) CR00 Capture Trigger Falling edge Rising ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer capture/compare register 01 (CR01) CR01 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or ...
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... TMC00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC00 to 00H. Caution 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 are set to values other than 0, 0 (operation stop mode), respectively. Clear TMC002 and TMC003 stop the operation. User’s Manual U17890EJ2V0UD ...
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... CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FF7EH After reset: 00H Symbol 7 6 TMC00 0 0 TMC003 TMC002 TMC001 Operating mode and clear mode selection Operation stop (TM00 cleared Free-running mode Clear & start occurs on TI000 ...
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... Cautions 1. Timer operation must be stopped before setting CRC00. 2. When the mode in which clear & start occurs on a match between TM00 and CR00 is selected with 16-bit timer mode control register 00 (TMC00), CR00 should not be specified as a capture register. 3. The capture operation is not performed if both the rising and falling edges are specified as the valid edge of the TI000 pin ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-7. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FF6BH After reset: 00H Symbol 7 <6> TOC00 0 OSPT00 OSPT00 0 No one-shot pulse trigger 1 One-shot pulse trigger OSPE00 0 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) This register is used to set the 16-bit timer counter 00 (TM00) count clock and valid edges of the TI000 and TI001 pin inputs. PRM00 can be set ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Cautions 1. When the internal low-speed oscillation clock is selected as the source clock to the CPU, the clock of the internal low-speed oscillator is divided and supplied as the count clock. If the ...
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... Set any value to the CR00 register. <3> Set the count clock by using the PRM00 register. <4> Set the TMC00 register to start the operation (see Figure 7-10 for the set value). Caution CR00 cannot be rewritten during TM00 operation. Remark For how to enable the INTTM00 interrupt, see CHAPTER 16 INTERRUPT FUNCTIONS. ...
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... CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-10. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (TMC00 TMC00 (b) Capture/compare control register 00 (CRC00 CRC00 ES101 ES100 ES001 ES000 PRM00 0/1 0/1 0/1 0/1 Remark 0/1: Setting allows another function to be used simultaneously with the interval timer. ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-11. Interval Timer Configuration Diagram Noise TI000/P53 eliminator f X Note OVF00 is set to 1 only when 16-bit timer capture/compare register ...
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... Set the TOC00 register (see Figure 7-13 for the set value). <5> Set the count clock by using the PRM00 register. <6> Set the TMC00 register to start the operation (see Figure 7-13 for the set value). Caution To change the value of the duty factor (the value of the CR01 register) during operation, see Caution 2 in Figure 7-15 PPG Output Operation Timing ...
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... CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-13. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 00 (TMC00 TMC003 TMC00 (b) Capture/compare control register 00 (CRC00 CRC00 (c) 16-bit timer output control register 00 (TOC00) 7 OSPT00 OSPE00 TOC004 LVS00 TOC00 0/1 (d) Prescaler mode register 00 (PRM00) ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-14. Configuration Diagram of PPG Output Noise TI000/P53 eliminator f X Figure 7-15. PPG Output Operation Timing Count clock TM00 count value ...
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... Set the CRC00 register (see Figures 7-17, 7-20, 7-22, and 7-24 for the set value). <2> Set the count clock by using the PRM00 register. <3> Set the TMC00 register to start the operation (see Figures 7-17, 7-20, 7-22, and 7-24 for the set value). Caution To use two capture registers, set the TI000 and TI001 pins. ...
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... TI000 pin is detected twice, thus eliminating noise with a short pulse width. Figure 7-17. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (When TI000 and CR01 Are Used) (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-18. Configuration Diagram for Pulse Width Measurement with Free-Running Counter TI000 Figure 7-19. Timing of Pulse Width Measurement Operation with Free-Running Counter ...
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... Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a capture operation is only performed when a valid level of the TI000 or TI001 pin is detected twice, thus eliminating noise with a short pulse width. Figure 7-20. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) 16-bit timer mode control register 00 (TMC00 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-21. Timing of Pulse Width Measurement Operation with Free-Running Counter t Count clock 0000H 0001H TM00 count value TI000 pin input CR01 capture value INTTM01 TI001 pin input CR00 capture value INTTM00 OVF00 ...
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... TI000 pin is detected twice, thus eliminating noise with a short pulse width. Figure 7-22. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-23. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM00 count value 0000H 0001H TI000 pin input CR01 capture value CR00 ...
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... CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-24. Control Register Settings for Pulse Width Measurement by Means of Restart (a) 16-bit timer mode control register 00 (TMC00 TMC00 (b) Capture/compare control register 00 (CRC00 CRC00 ES101 ES100 ES001 ES000 PRM00 0/1 0 Figure 7-25. Timing of Pulse Width Measurement Operation by Means of Restart ...
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... Set the count clock by using the PRM00 register. <3> Set any value to the CR00 register (0000H cannot be set). <4> Set the TMC00 register to start the operation (see Figure 7-26 for the set value). Remarks 1. For the setting of the TI000 pin, see 7.3 (5) Port mode register 5 (PM5). ...
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... CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-26. Control Register Settings in External Event Counter Mode (a) 16-bit timer mode control register 00 (TMC00 TMC00 (b) Capture/compare control register 00 (CRC00 CRC00 ES101 ES100 ES001 ES000 PRM00 0/1 0 Remark 0/1: Setting allows another function to be used simultaneously with the external event counter. ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-27. Configuration Diagram of External Event Counter Noise eliminator f X Valid edge of TI000 pin Note OVF00 is set to 1 only when CR00 is set to FFFFH. Figure 7-28. External Event ...
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... Set the TOC00 register (see Figure 7-29 for the set value). <4> Set any value to the CR00 register (0000H cannot be set). <5> Set the TMC00 register to start the operation (see Figure 7-29 for the set value). Caution CR00 cannot be rewritten during TM00 operation. ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-29. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 00 (TOC00) 7 OSPT00 OSPE00 TOC004 LVS00 TOC00 0/1 (d) Prescaler mode register 00 ...
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... FUNCTIONS. (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00), capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in Figure 7-31, and by setting bit 6 (OSPT00) of the TOC00 register software. ...
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... CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-31. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 00 (TMC00 TMC00 (b) Capture/compare control register 00 (CRC00 CRC00 (c) 16-bit timer output control register 00 (TOC00) 7 OSPT00 OSPE00 TOC004 TOC00 (d) Prescaler mode register 00 (PRM00) ...
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... Remark N < M (2) One-shot pulse output with external trigger A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00), capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in Figure 7-33, and by using the valid edge of the TI000 pin as an external trigger. ...
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... CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-33. Control Register Settings for One-Shot Pulse Output with External Trigger (a) 16-bit timer mode control register 00 (TMC00 TMC00 (b) Capture/compare control register 00 (CRC00 CRC00 (c) 16-bit timer output control register 00 (TOC00) 7 OSPT00 OSPE00 TOC004 TOC00 (d) Prescaler mode register 00 (PRM00) ...
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... CR01 set value N CR00 set value M TI000 pin input INTTM01 INTTM00 TO00 pin output Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC002 and TMC003 bits. Remark N < M 148 0000H User’s Manual U17890EJ2V0UD ...
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... Valid edge setting Set the valid edge of the TI000 pin after clearing bits 2 and 3 (TMC002 and TMC003) of 16-bit timer mode control register 00 (TMC00 respectively, and then stopping timer operation. The valid edge is set using bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00). ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (6) Operation of OVF00 flag <1> The OVF00 flag is also set the following case. When any of the following modes is selected: the mode in which clear & start occurs ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (8) Timer operation <1> Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare register 01 (CR01). <2> Regardless of the CPU’s operation mode, when the ...
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... Internal bus Selector Note 1 Match S Q INV OVF R Clear Note 2 S Invert level R TCE50 TMC506 LVS50 LVR50 TMC501 TOE50 8-bit timer mode control register 50 (TMC50) Internal bus User’s Manual U17890EJ2V0UD INTTM50 To TMH0 To UART0 TO50/TI50 /P50 Output latch PM50 (P50) ...
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... Figure 8-2. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus 8-bit timer compare register 51 (CR51) Match 8-bit timer OVF counter 51 (TM51 Clear 3 Selector TCL512 TCL511 TCL510 Timer clock selection register 51 (TCL51) Internal bus User’s Manual U17890EJ2V0UD Selector INTTM51 TCE51 TMC516 8-bit timer mode control register 51 (TMC51) 153 ...
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... When TM5n and CR5n match in the mode in which clear & start occurs upon a match of the TM5n and CR5n. 154 Configuration 8-bit timer counter 5n (TM5n) 8-bit timer compare register 5n (CR5n) TI50 TO50 Timer clock selection register 5n (TCL5n) 8-bit timer mode control register 5n (TMC5n) Port mode register 5 (PM5) Port register 5 (P5) After reset: 00H R User’s Manual U17890EJ2V0UD ...
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... Symbol CR5n ( Cautions 1. In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 = 0), do not write other values to CR5n during operation PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. ...
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... Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. Timer clock selection register 5n (TCL5n) 8-bit timer mode control register 5n (TMC5n) Port mode register 5 (PM5) Port register 5 (P5) (1) Timer clock selection register 5n (TCL5n) This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI50 pin input ...
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CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF3EH After reset: 00H Symbol 7 6 TCL51 0 0 TCL512 TCL511 ...
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... CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3> Timer output F/F (flip-flop) status setting < ...
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... Remarks 1. In PWM mode, PWM output is made inactive by clearing TCE50 LVS50 and LVR50 are read, the value The values of the TMC506, LVS50, LVR50, TMC501, and TOE50 bits are reflected at the TO50 pin regardless of the value of TCE50. Figure 8-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) ...
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CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode register 5 (PM5) This register sets port 5 input/output in 1-bit units. When using the P50/TO50/TI50 pins for timer output, clear PM50 and the output latches of P50 to ...
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... TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and CR5n. (TMC5n = 0000 <2> After TCE5n = 1 is set, the count operation starts. <3> If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). ...
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CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-10. Interval Timer Operation Timing (2/2) Count clock TM5n CR5n TCE5n INTTM5n t Count clock TM5n 01 CR5n FF TCE5n INTTM5n Remark 162 (b) When CR5n = ...
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... TI50 pin rising edge CR50: Compare value TMC50: Stop the count operation, select the mode in which clear & start occurs on match of TM50 and CR50, disable the timer F/F inversion operation, disable timer output. (TMC50 = 0000 <2> When TCE50 = 1 is set, the number of pulses input from the TI50 pin is counted. ...
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... Set each register. Clear the port output latch (P50) and port mode register (PM50 TCL50: Select the count clock. CR50: Compare value TMC50: Stop the count operation, select the mode in which clear & start occurs on a match of TM50 and CR50. LVS50 1 0 ...
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... The duty pulse determined by the value set to 8-bit timer compare register 50 (CR50) is output from TO50. Set the active level width of the PWM pulse to CR50; the active level can be selected with bit 1 (TMC501) of TMC50. The count clock can be selected with bits (TCL500 to TCL502) of timer clock selection register 50 (TCL50). ...
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... Set each register. Clear the port output latch (P50) and port mode register (PM50 TCL50: Select the count clock. CR50: Compare value TMC50: Stop the count operation, select PWM mode. The timer output F/F is not changed. TMC501 0 1 Timer output enabled (TMC50 = 01000001B or 01000011B) < ...
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CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-13. PWM Output Operation Timing (a) Basic operation (active level = H) t Count clock TM50 00H 01H FFH 00H 01H 02H CR50 N TCE50 INTTM50 TO50 <1> t Count clock ...
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CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR50 changed Figure 8-14. Timing of Operation with CR50 Changed (a) CR50 value is changed from before clock rising edge of FFH Value is transferred to ...
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CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error one clock may occur in the time required for a match signal to be ...
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Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) ...
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Table 9-2. Option Byte Setting and Watchdog Timer Operation Mode Internal Low-speed Oscillator Cannot Be Stopped Note 1 Watchdog timer clock Fixed source Operation after reset Operation starts with the maximum interval ...
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Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 9-3. Configuration of Watchdog Timer Item Control registers Figure 9-1. Block Diagram of Watchdog Timer 2 Clock 16-bit input counter ...
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Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock ...
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Cautions 1. If data is written to WDTM, a wait cycle is generated. For details, see CHAPTER 27 CAUTIONS FOR WAIT. 2. Set bits 7, 6, and and 1, respectively (when “Internal low-speed oscillator cannot be ...
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Operation of Watchdog Timer 9.4.1 Watchdog timer operation when “Internal low-speed oscillator cannot be stopped” is selected by option byte The operation clock of watchdog timer is fixed to the internal low-speed oscillation clock. After reset is released, operation ...
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Watchdog timer operation when “Internal low-speed oscillator can be stopped by software” is selected by option byte The operation clock of the watchdog timer can be selected as either the internal low-speed oscillation clock or the X1 input clock. ...
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Watchdog timer operation in STOP mode (when “Internal low-speed oscillation can be stopped by software” is selected by option byte) The watchdog timer stops counting during STOP instruction execution regardless of whether the X1 input clock or internal low-speed ...
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When the CPU clock is the internal low-speed oscillation clock (f clock is the X1 input clock (f ) when the STOP instruction is executed XP When the STOP instruction is executed, operation of the watchdog timer is stopped. ...
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When CPU clock and watchdog timer operation clock are the internal low-speed oscillation clocks (f during STOP instruction execution When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is ...
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CHAPTER 10 REAL-TIME OUTPUT PORT 10.1 Function of Real-Time Output Port Data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupts request generation, then output externally. This is ...
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Real-time output port 1 (6 bits Real-time output port <R> control register 1 (RTPC01) RTPOE01 BYTE01 2 Output trigger INTTM01 (from TM00) (from 10-bit inverter Remark CHAPTER 10 REAL-TIME OUTPUT PORT Figure 10-1. Block Diagram ...
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Real-time output buffer register 1 (RTBL01, RTBH01) This register consists of two 4-bit Note registers that hold output data in advance. The addresses of RTBL01 and RTBH01 are mapped individually in the special function register (SFR) area as shown ...
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Registers Controlling Real-Time Output Port The following four types of registers control the real-time output ports. • Real-time output port mode register 1(RTPM01) • Real-time output port control register 1 (RTPC01) • DC control register 01 (DCCTL01) • PWM ...
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Real-time output port control register 1 (RTPC01) This register is used to set the operation mode, and enabling or disabling operation of the real-time output port. The outputs to be set are RTP10 to RTP15. The relationship between the ...
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... PWM modulation enabled INV01 0 Inversion disabled 1 Inversion enabled Note The PWM signal uses the inverter timer outputs (TW0TO0 or TW0TO0 to TW0TO5). Remarks 1. The outputs to be set are RTP10 to RTP15. 2. The PWMCH01, PWMCL01, and INV01 settings are valid only when DCEN01 = 1. R INV01 0 ...
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PWM select register (DCCTL02) This register selects the PWM signal during the PWM modulation operation. DCCTL02 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 10-6. Format of PWM Select ...
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... RTP15 possible to use RTP10 to RTP15 as inverter timer output when inverter timer output is specified by DCEN01. The operation mode can be selected as 6 bits By setting INV01 possible to invert the output waveform. Also, by setting PWMCL01 and PWMCH01 possible to perform PWM modulation of the output pattern. If real-time output was disabled (RTPOE01 = 0) when RTPM01n = 1 and INV01 = 0, then RTP10 to RTP15 output TW0TO0 or TW0TO0 to TW0TO5 ...
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... Bit 7 of inverter timer control register (TW0C) DCEN01: Bit control register 01 (DCCTL01) INV01: Bit 4 of DCCTL01 PWMCH01: Bit 6 of DCCTL01 PWMCL01: Bit 5 of DCCTL01 RTPOE01: Bit 7 of real-time output port control register 1 (RTPC01) RTPM01n: Bit n of real-time output port mode register 1 (RTPM01) ...
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... Figure 10-7. Real-Time Output Port Operation Timing Example (6 Bits (a) 6 bits 1 channel, inverted output disabled, no PWM modulation (BYTE01 = 1, INV01 = 0, PWMCH01 = 0, PWMCL01 = 0) INTTM01 CPU A A Operation RTBH01, 01H 02H RTBL01 Output latch 01H 02H TW0TO0 to TW0TO5 Output latch TW0TO0 Output latch TW0TO1 ...
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... Figure 10-7. Real-Time Output Port Operation Timing Example (6 Bits (b) 6 bits 1 channel, inverted output enabled, no PWM modulation (BYTE01 = 1, INV01 = 1, PWMCH01 = 0, PWMCL01 = 0) INTTM01 CPU A A Operation RTBH01, 01H 02H RTBL01 Output latch 01H 02H TW0TO0 to TW0TO5 Output latch TW0TO0 Output latch TW0TO1 ...
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... CHAPTER 10 REAL-TIME OUTPUT PORT Figure 10-7. Real-Time Output Port Operation Timing Example (6 Bits (c) 6 bits 1 channel, inverted output enabled, PWM modulation (BYTE01 = 1, INV01 = 1, PWMCH01 = 1, PWMCL01 = 1) INTTM01 CPU A A Operation RTBH01, 01H 02H RTBL01 Output latch 01H 02H TW0TO0 to TW0TO5 Output latch ...
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Using Real-Time Output Port When using the real-time output port, perform the following steps. (1) Disable real-time output operation. Clear bit 7 (RTPOE01) of real-time output port control register 1 (RTPC01 (2) Initial setting • Specify the ...
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Notes on Real-Time Output Port (1) Before performing the initial setting, disable the real-time output operation by clearing bit 7 (RTPOE01) of real- time output port control register 1 (RTPC01 (2) Once the real-time output operation has ...
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CHAPTER 11 DC INVERTER CONTROL FUNCTION The PD78F0711 and 78F0712 realize a 3-phase PWM DC inverter control by combination of 10-bit inverter control timer and real-time output port. See the following chapters. CHAPTER 6 10-BIT INVERTER CONTROL TIMER CHAPTER10 REAL-TIME ...
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Hi-Z Output Controller Functions The Hi-Z output controller can forcibly stop all output signals of the three-phase inverter control timer detects an abnormality in the motor, by inputting an abnormality detection signal to the TW0TOFFP pin. Function ...
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Register for Controlling Hi-Z Output Controller (1) High-impedance output control register 0 (HZA0CTL0) The HZA0CTL0 register is an 8-bit register that controls the high-impedance state of the output buffer of the TW0TO0 to TW0TO5 pins. This register is set ...
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CHAPTER 12 Hi-Z OUTPUT CONTROLLER Figure 12-2. Format of High-impedance Output Control Register 0 (2/2) High-impedance output control clear bit HZA0DCC0 0 No operation 1 A target pin in the high-impedance state is enabled by using software to output a ...
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Operation of Hi-Z Output Controller (1) To set high-impedance control operation <Procedure> <1> Set the HZA0DCM0, HZA0DCN0, and HZA0DCP0 bits. <2> Set the HZA0DCE0 bit to 1 (to enable high-impedance control). (2) To change setting after enabling high-impedance control ...