MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 102

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(1) 10-bit up/down counter (TW0UDC)
(2) 10-bit compare registers 0 to 2 (TW0CM0 to TW0CM2)
(3) 10-bit compare register 3 (TW0CM3)
(4) 10-bit compare registers 4, 5 (TW0CM4, TW0CM5)
100
TW0UDC is a 10-bit up/down counter that counts count pulses in synchronization with the rising edge of the
count clock. When the timer starts, the number of count pulse count is incremented from 0, and when the value
preset to compare register 3 (TW0CM3) and TW0UDC count value match, it is switched to the count down
operation.
An underflow signal is generated if the value becomes 000H during the count down operation and interrupt
request signal INTTW0UD is generated. When an underflow occurs, it is switched from the count down operation
to the count up operation. INTTW0UD is normally generated at every underflow but the number of occurrences
can be divided by the IDEV00 to IDEV02 bits of inverter timer control register (TW0C).
TW0UDC cannot be read/written.
The cycle of TW0UDC is controlled by TM0CM3.
The count clock can be selected from 6 types: f
RESET input or clearing the CE0 bit of TW0C7 sets TW0UDC to 000H.
TW0CM0 to TW0CM2 are 10-bit compare registers that always compare their own value with that of TW0UDC,
and if they match, the contents of the flip-flops are changed.
Each of TW0CM0 to TW0CM2 are provided with a buffer register (TW0BFCM0 to TW0BFCM2), so that the
contents of the buffer can be transferred to TW0CM0 to TW0CM2 at the timing of interrupt request signal
INTTW0UD generation.
A write operation to TW0CM0 to TW0CM2 is possible only while TW0UDC is stopped.
To set the output timing, write data to TW0BFCM0 to TW0BFCM2.
RESET input or clearing the CE0 bit of TW0C sets these registers to 000H.
TW0CM3 is a 10-bit compare register that controls the high limit value of TW0UDC. If the count value of
TW0UDC matches the value of TW0CM3 or 0, count up/down is switched at the next count clock.
TW0CM3 provides a buffer register (TW0BFCM3) whose contents are transferred to TW0CM3 at the timing of
interrupt request signal INTTW0UD generation.
TW0CM3 can be written to only while TW0UDC is stopped.
To set the cycle to TW0UDC, write data to TW0BFCM3.
RESET input sets TW0CM3 to 0FFH.
Do not set TW0CM3 to 000H.
TW0CM4 and TW0CM5 are 10-bit compare registers that always compare their own value with that of TW0UDC,
and if they match, interrupt request signal is generated.
Each of TW0CM4 and TW0CM5 are provided with a buffer register (TW0BFCM4, TW0BFCM5), so that the
contents of the buffer can be transferred to TW0CM4 to TW0CM5 at the timing of interrupt request signal
INTTW0UD generation.
A write operation to TW0CM4 and TW0CM5 is possible only while TW0UDC is stopped.
To set the output timing, write data to TW0BFCM4 and TW0BFCM5.
RESET input or clearing the CE0 bit of TW0C sets these registers to 000H.
CHAPTER 6 10-BIT INVERTER CONTROL TIMER
User’s Manual U17890EJ2V0UD
X
, f
X
/2, f
X
/4, f
X
/8, f
X
/16, f
X
/32.