MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 308

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MC-78F0712-KIT

Manufacturer Part Number
MC-78F0712-KIT
Description
KIT REF SYSTEM 78K0 UPD78F0712
Manufacturer
Renesas Electronics America
Datasheets

Specifications of MC-78F0712-KIT

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
306
Note 1
If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
Notes 1.
2.
No
If reset is generated again during this period, initialization processing is not started.
A flowchart is shown on the next page.
Figure 20-5. Example of Software Processing After Release of Reset (1/2)
50 ms has passed?
Change CPU clock
Check stabilization
Checking cause
(TMIF51 = 1?)
(set to 50 ms)
of oscillation
of reset
Initialization
processing
Start timer
Reset
LVI
Yes
Note 2
CHAPTER 20 LOW-VOLTAGE DETECTOR
User’s Manual U17890EJ2V0UD
; The internal low-speed oscillation
;
;
;
;
;
;
The cause of reset (power-on-clear, WDT, or LVI)
can be identified by the RESF register.
8-bit timer 51 can operate with the
Source: f
(f
Check the stabilization of oscillation of the X1 input clock by using the
OSTC register.
Change the CPU clock from the
TMIF51 = 1: Interrupt request is generated.
Initialization of ports
the reset signal is generated
the X1 input clock.
RL
:
Internal low-speed oscillation
RL
(480 kHz (MAX.))/2
7
internal low-speed oscillation
clock is set as the CPU clock when
compare value 200 = 53 ms
clock oscillation frequency)
internal low-speed oscillation
clock to
clock.

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