MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 178

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.4.2
input clock.
the watchdog timer mode register (WDTM) = 1, 1, 1).
operation in STOP mode and 9.4.4 Watchdog timer operation in HALT mode.
176
The operation clock of the watchdog timer can be selected as either the internal low-speed oscillation clock or the X1
After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
The following shows the watchdog timer operation after reset release.
1.
2.
3.
Notes 1.
Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution.
For the watchdog timer operation during STOP mode and HALT mode in each status, see 9.4.3 Watchdog timer
The status after reset release is as follows.
The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instruction
After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Watchdog timer operation when “Internal low-speed oscillator can be stopped by software” is selected
by option byte
Operation clock: Internal low-speed oscillation clock (f
Cycle: f
Counting starts
Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4).
Internal low-speed oscillation clock (f
X1 input clock (f
Watchdog timer operation stopped
Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
2.
3.
After HALT/STOP mode is released, counting is started again using the operation clock of the
watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter
is not cleared to 0 but holds its value.
As soon as WDTM is written, the counter of the watchdog timer is cleared.
Set bits 7, 6, and 5 to 0, 1, 1, respectively. Do not set the other values.
If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and , respectively, an internal
reset signal is not generated even if the following processing is performed.
Notes 1, 2, 3
WDTM is written a second time.
A 1-bit memory manipulation instruction is executed to WDTE.
A value other than ACH is written to WDTE.
RL
/2
18
(1.09 seconds: At operation with f
.
XP
)
CHAPTER 9 WATCHDOG TIMER
RL
User’s Manual U17890EJ2V0UD
)
RL
= 240 kHz (TYP.))
RL
)