MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 278
MC-78F0712-KIT
Manufacturer Part Number
MC-78F0712-KIT
Description
KIT REF SYSTEM 78K0 UPD78F0712
Manufacturer
Renesas Electronics America
Specifications of MC-78F0712-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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(2) STOP mode
set are held. The I/O port output latches and output buffer statuses are also held.
276
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is
Cautions 1. STOP and HALT mode can be used when CPU is operating on the high-speed system clock
STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock stops,
stopping the whole system, thereby considerably reducing the CPU operating current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is
released, select the HALT mode if it is necessary to start processing immediately upon interrupt request
generation.
2. Setting in the STOP mode is prohibited when the internal high-speed oscillation clock is
3. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before
4. The following sequence is recommended for operating current reduction of the A/D converter
5. If the internal low-speed oscillator is operating before the STOP mode is set, oscillation of the
or internal low-speed oscillation clock. However, when the STOP instruction is executed
during internal low-speed oscillation clock operation, the X1 or internal high-speed oscillator
stops, but internal low-speed oscillator does not stop.
operating. In this case, switch to the internal low-speed oscillation clock before setting in the
STOP mode.
executing STOP instruction.
when the standby function is used: First clear bit 7 (ADCS) of the A/D converter mode
register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP
instruction.
internal low-speed oscillation clock cannot be stopped in the STOP mode. However, when
the internal low-speed oscillation clock is used as the CPU clock, the CPU operation is
stopped for 21/f
RL
(s) after STOP mode is released.
CHAPTER 17 STANDBY FUNCTION
User’s Manual U17890EJ2V0UD
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