MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 81

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(4) Main clock mode register (MCM)
This register selects the main system clock (f
The main system clock becomes a source clock to the CPU and the peripheral hardware.
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: FFA1H
Symbol
MCM
Caution When internal low-speed oscillation clock is selected as the source clock to the
Note Bit 1 is read-only.
MCM0
MCS
7
0
0
1
0
1
After reset: 00H
CPU, the divided clock of the internal low-speed oscillation clock (f
the peripheral hardware (f
However, operation of the peripheral hardware with the internal low-speed
oscillation clock cannot be guaranteed. Therefore, when the internal low-speed
oscillation clock is selected as the source clock to the CPU, do not use the
peripheral hardware. In addition, stop the peripheral hardware before switching the
source clock to the CPU from the high-speed system clock to the internal low-speed
oscillation clock. Note, however, that the following peripheral hardware can be used
when the CPU operates on the internal low-speed oscillation clock.
Figure 5-5. Format of Main Clock Mode Register (MCM)
Operates with internal low-speed oscillation clock
Operates with high-speed system clock
Internal low-speed oscillation clock (f
High-speed system clock (f
Watchdog timer (when internal low-speed oscillation is selected)
8-bit timer 51 (when f
Peripheral hardware selecting external clock as the clock source
(Except 16-bit timer/event counter 00)
6
0
R/W
CHAPTER 5 CLOCK GENERATOR
Note
Selection of source clock to CPU (main system clock (f
User’s Manual U17890EJ2V0UD
Status of source clock to CPU (main system clock (f
5
0
XP
).
XH
RL
)
RL
= 240 kHz (TYP.)).
/2
4
0
7
is selected as count clock)
RL
)
3
0
2
0
XP
MCS
<1>
XP
) )
))
RL
) is supplied to
MCM0
<0>
79