MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 103

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(5) 10-bit buffer registers 0 to 5 (TW0BFCM0 to TW0BFCM5)
(7) Dead-time timers 0 to 2 (DTM0 to DTM2)
(8) Buffer transfer control timer (RTM0)
(6) Dead-time reload register (TW0DTIME)
TW0BFCM0 to TW0BFCM5 are 10-bit registers. They transfer data to the compare register (TW0CM0 to
TW0CM5) corresponding to each buffer register at the timing of interrupt request signal INTTW0UD generation.
TW0BFCM0 to TW0BFCM5 can be read/written irrespective of whether TW0UDC count is stopped or operating.
RESET input sets TW0BFCM0 to TW0BFCM2, TW0BFCM4 and TW0BFCM5 to 000H, and TW0BFCM3 to
0FFH.
These registers can be read/written in word and byte units. For read/write operations of less than 8 bits,
TW0BFCM0L to TW0BFCM5L are used.
TW0DTIME is an 8-bit register to set dead time and is common to three dead-time timers (DTM0 to DTM2).
However, the data load timing from TW0DTIME to DTM0, DTM1 and DTM2 is independent.
TW0DTIME can be written only while TW0UDC counting is stopped. Data does not change even if an instruction
to rewrite TW0DTIME is executed during timer operation.
RESET input sets TW0DTIME to FFH.
Even if TW0DTIME is set to 00H, an output with the dead time of 1/f
DTM0 to DTM2 are 8-bit down counters that generate dead time.
Count down is performed after the value of the dead-time reload register (TW0DTIME) is reloaded with the timing
of a compare match between TW0CM0 to TW0CM2 and TW0UDC. DTM0 to DTM2 generate an underflow signal
when 00H changes to FFH and stop with FFH.
The count clock is f
DTM0 to DTM2 cannot be read/written.
RESET input or clearing the CE0 bit of TW0C sets these registers to FFH.
RTM0 is a 3-bit up counter. It has the function of dividing interrupt request signal INTTW0UD.
Incrementing is performed with the TW0UDC underflow signal and INTTW0UD is generated when the value
matches the number of divisions set with bits IDEV00 to IDEV02 of TW0C.
RTM0 cannot be read/written.
RESET input sets RTM0 to 7H. Generating INTTW0UD and clearing the CE0 bit of TW0C also sets RTM0 to 7H.
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CHAPTER 6 10-BIT INVERTER CONTROL TIMER
User’s Manual U17890EJ2V0UD
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is performed.
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