MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 131

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MC-78F0712-KIT

Manufacturer Part Number
MC-78F0712-KIT
Description
KIT REF SYSTEM 78K0 UPD78F0712
Manufacturer
Renesas Electronics America
Datasheets

Specifications of MC-78F0712-KIT

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Cautions 1. Values in the following range should be set in CR00 and CR01:
Remark
TMC00
TOC00
PRM00
CRC00
ES101
0/1
2. The cycle of the pulse generated through PPG output (CR00 setting value + 1) has a duty of
7
0
7
0
7
0
: Don’t care
0000H
(CR01 setting value + 1)/(CR00 setting value + 1).
OSPT00
ES100
0/1
0
6
0
6
0
Figure 7-13. Control Register Settings for PPG Output Operation
OSPE00
ES001
0/1
CR01 < CR00
0
5
0
5
0
TOC004
ES000
(c) 16-bit timer output control register 00 (TOC00)
(a) 16-bit timer mode control register 00 (TMC00)
(b) Capture/compare control register 00 (CRC00)
0/1
1
4
0
4
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
LVS00
(d) Prescaler mode register 00 (PRM00)
TMC003
0/1
1
3
0
3
0
FFFFH
LVR00
TMC002
CRC002
0/1
User’s Manual U17890EJ2V0UD
1
0
0
2
TOC001
TMC001
CRC001 CRC000
PRM001
1
0/1
0
TOE00
OVF00
PRM000
1
0/1
0
0
Enables TO00 output.
Inverts output on match between TM00 and CR00.
Specifies initial value of TO00 output F/F (setting “11” is prohibited).
Inverts output on match between TM00 and CR01.
Disables one-shot pulse output.
Clears and starts on match between TM00 and CR00.
CR00 used as compare register
CR01 used as compare register
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
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