MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 181
MC-78F0712-KIT
Manufacturer Part Number
MC-78F0712-KIT
Description
KIT REF SYSTEM 78K0 UPD78F0712
Manufacturer
Renesas Electronics America
Specifications of MC-78F0712-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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(4) When CPU clock and watchdog timer operation clock are the internal low-speed oscillation clocks (f
9.4.4
X1 input clock (f
the X1 input clock (f
again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but
holds its value.
The watchdog timer stops counting during HALT instruction execution regardless of whether the CPU clock is the
CPU operation
CPU operation
during STOP instruction execution
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0 but holds its value.
Watchdog timer
Watchdog timer
Watchdog timer operation in HALT mode (when “Internal low-speed oscillation can be stopped by
software” is selected by option byte)
XP
f
f
f
f
(internal low-speed
XP
XP
RL
RL
Normal operation
) or internal low-speed oscillation clock (f
(CPU Clock and WDT Operation Clock: Internal Low-speed Oscillation Clock)
Normal operation
oscillation clock)
XP
) or internal low-speed oscillation clock (f
Operating
Operating Operation stopped
Operation stopped
Oscillation
stopped
STOP
HALT
Figure 9-7. Operation in STOP Mode
Figure 9-8. Operation in HALT Mode
CHAPTER 9 WATCHDOG TIMER
User’s Manual U17890EJ2V0UD
Clock supply stopped
Oscillation stabilization time
(set by OSTS register)
17 clocks
RL
), or whether the operation clock of the watchdog timer is
Operating
RL
). After HALT mode is released, counting is started
Normal operation
(internal low-speed oscillation clock)
Operating
Normal operation
179
RL
)
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