MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 335

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8-bit
operation
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
3.
OR
XOR
CMP
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Except “r = A”
control register (PCC).
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
CHAPTER 24 INSTRUCTION SET
Note 3
Note 3
Note 3
User’s Manual U17890EJ2V0UD
Bytes
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
Note 1
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
Clocks
Note 2
8
5
9
5
9
9
9
8
5
9
5
9
9
9
8
5
9
5
9
9
9
A
(saddr)
A
r
A
A
A
A
A
A
A
(saddr)
A
r
A
A
A
A
A
A
A
(saddr)
A
r
A
A
A
A
A
A
A
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
(HL + B)
(HL + C)
r
r
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
(HL + B)
(HL + C)
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
(HL + B)
(HL + C)
byte
(saddr)
(saddr)
CPU
) selected by the processor clock
Operation
byte
byte
Z AC CY
Flag
333