MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 92

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

90
Notes 1.
2.
3.
4.
(2) When “Internal low-speed oscillator cannot be stopped” is selected by option byte
CPU clock: f
f
f
XP
RL
In the case of the X1 clock, check the oscillation stabilization time status using the oscillation
stabilization time counter status register (OSTC) before shifting from status 2 to status 3 after reset
and STOP are released. In the case of the internal high-speed oscillation clock, secure wait time
(350 s) by software.
When shifting from status 2 to status 1, make sure that MCS is 0.
The watchdog timer operates using internal low-speed oscillation clock even in STOP mode if
“Internal low-speed oscillator cannot be stopped” is selected by an option byte. Internal low-speed
oscillation clock division can be selected as the count source of 8-bit timer 51 (TM51), so clear the
watchdog timer using the TM51 interrupt request before watchdog timer overflow. If this processing
is not performed, an internal reset signal is generated at watchdog timer overflow after STOP
instruction execution.
All reset sources (RESET input, POC, LVI, and WDT)
: Oscillating
: Oscillating
Status 3
XP
instruction
Interrupt
STOP
MCM0 = 1
MCM0 = 0
Figure 5-12. Status Transition Diagram (2/2)
Interrupt
HALT
instruction
CHAPTER 5 CLOCK GENERATOR
Note 1
User’s Manual U17890EJ2V0UD
instruction
Interrupt
STOP
CPU clock: f
f
f
XP
RL
STOP
: Oscillating
: Oscillating
Status 2
HALT
Note 3
HALT
instruction
Interrupt
RL
Interrupt
instruction
MSTOP = 1
MSTOP = 0
STOP
Reset release
HALT instruction
Interrupt
Note 2
f
XP
: Oscillation stopped
CPU clock: f
f
Reset
RL
: Oscillating
Status 1
Note 4
RL