MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 268

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MC-78F0712-KIT

Manufacturer Part Number
MC-78F0712-KIT
Description
KIT REF SYSTEM 78K0 UPD78F0712
Manufacturer
Renesas Electronics America
Datasheets

Specifications of MC-78F0712-KIT

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN)
Address: FF48H
Symbol
EGP
Address: FF49H
Symbol
EGN
266
Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be detected when
Remark n = 0 to 3, 5
These registers specify the valid edge for INTP0 to INTP3, and INTP5.
EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Table 16-3 shows the ports corresponding to EGPn and EGNn.
the external interrupt function is switched to the port function.
EGPn
Detection Enable Register
7
0
7
0
0
0
1
1
After reset: 00H
After reset: 00H
Figure 16-5. Format of External Interrupt Rising Edge Enable Register (EGP)
EGP0
EGP1
EGP2
EGP3
EGP5
EGNn
6
0
6
0
0
1
0
1
Table 16-3. Ports Corresponding to EGPn and EGNn
and External Interrupt Falling Edge Enable Register (EGN)
EGN0
EGN1
EGN2
EGN3
EGN5
R/W
R/W
Edge detection disabled
Falling edge
Rising edge
Both rising and falling edges
EGN5
CHAPTER 16 INTERRUPT FUNCTIONS
EGP5
5
5
P00
P01
P02
P03
P53
User’s Manual U17890EJ2V0UD
Edge Detection Port
INTPn pin valid edge selection (n = 0 to 3, 5)
4
0
4
0
EGN3
EGP3
3
3
INTP0
INTP1
INTP2
INTP3
INTP5
EGN2
EGP2
2
2
Interrupt Request Signal
EGN1
EGP1
1
1
EGP0
EGN0
0
0

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