ATMEGA32A-PU Atmel, ATMEGA32A-PU Datasheet - Page 169

• Manufacturer Part Number: ATMEGA32A-PU
• Description: MCU AVR 32K FLASH 16MHZ 40-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Rom Size: 1024 B
• Height: 4.83 mm
• Length: 52.58 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 13.97 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.11.3
8155C–AVR–02/11
UCSRB – USART Control and Status Register B
• Bit 0 – MPCM: Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCM bit is written to
one, all the incoming frames received by the USART receiver that do not contain address infor-
mation will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed
information see
• Bit 7 – RXCIE: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC Flag. A USART Receive Complete Interrupt
will be generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is writ-
ten to one and the RXC bit in UCSRA is set.
• Bit 6 – TXCIE: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC Flag. A USART Transmit Complete Interrupt
will be generated only if the TXCIE bit is written to one, the Global Interrupt Flag in SREG is writ-
ten to one and the TXC bit in UCSRA is set.
• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDRE Flag. A Data Register Empty Interrupt will
be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written
to one and the UDRE bit in UCSRA is set.
• Bit 4 – RXEN: Receiver Enable
Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-
ation for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FE, DOR, and PE Flags.
• Bit 3 – TXEN: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXEN to zero)
will not become effective until ongoing and pending transmissions are completed, that is, when
the transmit Shift Register and transmit Buffer Register do not contain data to be transmitted.
When disabled, the transmitter will no longer override the TxD port.
• Bit 2 – UCSZ2: Character Size
The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Char-
acter Size) in a frame the receiver and transmitter use.
• Bit 1 – RXB8: Receive Data Bit 8
RXB8 is the ninth data bit of the received character when operating with serial frames with nine
data bits. Must be read before reading the low bits from UDR.
Bit
Read/Write
Initial Value
RXCIE
“Multi-processor Communication Mode” on page
R/W
7
0
TXCIE
R/W
6
0
UDRIE
R/W
5
0
RXEN
R/W
4
0
TXEN
R/W
3
0
UCSZ2
R/W
2
0
164.
RXB8
R
1
0
ATmega32A
TXB8
R/W
0
0
UCSRB
169