ATMEGA32A-PU Atmel, ATMEGA32A-PU Datasheet - Page 244

• Manufacturer Part Number: ATMEGA32A-PU
• Description: MCU AVR 32K FLASH 16MHZ 40-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Rom Size: 1024 B
• Height: 4.83 mm
• Length: 52.58 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 13.97 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 24-5.
8155C–AVR–02/11
Signal
Name
COMP
ACLK
ACTEN
ADCBGEN
ADCEN
AMPEN
DAC_9
DAC_8
DAC_7
DAC_6
DAC_5
DAC_4
DAC_3
DAC_2
DAC_1
DAC_0
EXTCH
G10
G20
GNDEN
HOLD
IREFEN
MUXEN_7
MUXEN_6
MUXEN_5
MUXEN_4
MUXEN_3
Boundary-scan Signals for the ADC
Direction as Seen
from the ADC
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Comparator Output
Clock signal to gain stages
implemented as Switch-cap filters
Enable path from gain stages to
the comparator
Enable Band-gap reference as
negative input to comparator
Power-on signal to the ADC
Power-on signal to the gain stages
Bit 9 of digital value to DAC
Bit 8 of digital value to DAC
Bit 7 of digital value to DAC
Bit 6 of digital value to DAC
Bit 5 of digital value to DAC
Bit 4 of digital value to DAC
Bit 3 of digital value to DAC
Bit 2 of digital value to DAC
Bit 1 of digital value to DAC
Bit 0 of digital value to DAC
Connect ADC channels 0 - 3 to by-
pass path around gain stages
Enable 10x gain
Enable 20x gain
Ground the negative input to
comparator when true
Sample&Hold signal. Sample
analog signal when low. Hold
signal when high. If gain stages
are used, this signal must go
active when ACLK is high.
Enables Band-gap reference as
AREF signal to DAC
Input Mux bit 7
Input Mux bit 6
Input Mux bit 5
Input Mux bit 4
Input Mux bit 3
Recommended
Input when Not
in Use
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
Output Values when Recommended
Inputs are used, and CPU is not
Using the ADC
ATmega32A
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
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