ATMEGA32A-PU Atmel, ATMEGA32A-PU Datasheet - Page 84

• Manufacturer Part Number: ATMEGA32A-PU
• Description: MCU AVR 32K FLASH 16MHZ 40-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Rom Size: 1024 B
• Height: 4.83 mm
• Length: 52.58 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 13.97 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.9
14.9.1
8155C–AVR–02/11
Register Description
TCCR0 – Timer/Counter Control Register
Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres-
• Bit 7 – FOC0: Force Output Compare
The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However, for
ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written
when operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate com-
pare match is forced on the Waveform Generation unit. The OC0 output is changed according to
its COM0[1:0] bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the
value present in the COM0[1:0] bits that determines the effect of the forced compare.
A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0 as TOP.
The FOC0 bit is always read as zero.
• Bit 6, 3 – WGM0[1:0]: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of Waveform Generation to be used. Modes of operation sup-
ported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare Match (CTC)
mode, and two types of Pulse Width Modulation (PWM) modes. See
Operation” on page
Bit
Read/Write
Initial Value
TCNTn
(clk
(CTC)
OCRn
OCFn
clk
clk
I/O
I/O
Tn
/8)
caler (f
FOC0
W
7
0
78.
clk_I/O
WGM00
TOP - 1
R/W
/8)
6
0
COM01
R/W
5
0
COM00
R/W
TOP
4
0
WGM01
TOP
R/W
3
0
CS02
R/W
BOTTOM
2
0
Table 14-2
CS01
R/W
1
0
ATmega32A
BOTTOM + 1
CS00
R/W
0
0
and
“Modes of
TCCR0
84