ATMEGA32A-PU Atmel, ATMEGA32A-PU Datasheet - Page 260

• Manufacturer Part Number: ATMEGA32A-PU
• Description: MCU AVR 32K FLASH 16MHZ 40-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Rom Size: 1024 B
• Height: 4.83 mm
• Length: 52.58 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 13.97 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.8.3
25.8.4
25.8.5
25.8.6
25.8.7
8155C–AVR–02/11
Performing a Page Write
Using the SPM Interrupt
Consideration while Updating BLS
Prevent Reading the RWW Section during Self-Programming
Setting the Boot Loader Lock Bits by SPM
To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCR and
execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to
zero during this operation.
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the
SPMEN bit in SPMCR is cleared. This means that the interrupt can be used instead of polling
the SPMCR Register in software. When using the SPM interrupt, the Interrupt Vectors should be
moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is
blocked for reading. How to move the interrupts is described in
Special care must be taken if the user allows the Boot Loader section to be updated by leaving
Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the
entire Boot Loader, and further software updates might be impossible. If it is not necessary to
change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to
protect the Boot Loader software from any internal software changes.
During Self-Programming (either Page Erase or Page Write), the RWW section is always
blocked for reading. The user software itself must prevent that this section is addressed during
the Self-Programming operation. The RWWSB in the SPMCR will be set as long as the RWW
section is busy. During self-programming the Interrupt Vector table should be moved to the BLS
as described in
the RWW section after the programming is completed, the user software must clear the
RWWSB by writing the RWWSRE. See
page 261
To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCR and
execute SPM within four clock cycles after writing SPMCR. The only accessible Lock bits are the
Boot Lock bits that may prevent the Application and Boot Loader section from any software
update by the MCU.
See
Flash access.
If bits 5:2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an
SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCR.
The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to
load the Z-pointer with $0001 (same as used for reading the Lock bits). For future compatibility It
is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock bits. When pro-
gramming the Lock bits the entire Flash can be read during the operation.
Bit
R0
• Page Write to the RWW section: The NRWW section can be read during the Page Write.
• Page Write to the NRWW section: The CPU is halted during the operation.
Table 25-2
for an example.
“Interrupts” on page
and
7
1
Table 25-3
6
1
for how the different settings of the Boot Loader bits affect the
BLB12
5
45, or the interrupts must be disabled. Before addressing
“Simple Assembly Code Example for a Boot Loader” on
BLB11
4
BLB02
3
BLB01
“Interrupts” on page
2
ATmega32A
1
1
0
1
45.
260