P89V51RC2FN,112 NXP Semiconductors, P89V51RC2FN,112 Datasheet - Page 42

• Manufacturer Part Number: P89V51RC2FN,112
• Description: IC 80C51 MCU FLASH 32K 40-DIP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V51RC2FN,112

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1017 - BOARD 44-ZIF PLCC SOCKET622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2430-5; 935278782112; P89V51RC2FN

NXP Semiconductors
P89V51RB2_RC2_RD2_5
Product data sheet
6.7.1 SPI features
6.7.2 SPI description
6.7 SPI
In a more complex system the following could be used to select slaves 1 and 2 while
excluding slave 0:
Example 1, slave 0:
Example 2, slave 1:
Example 3, slave 2:
In the above example the differentiation among the 3 slaves is in the lower 3 address bits.
Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1
requires that bit 1 = 0 and it can be uniquely addressed by 1110 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude
Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the logical OR of SADDR and
SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the
don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR
and SADEN are loaded with 0s. This produces a given address of all ‘don’t cares’ as well
as a Broadcast address of all ‘don’t cares'. This effectively disables the Automatic
Addressing mode and allows the microcontroller to use standard UART drivers which do
not make use of this feature.
The SPI allows high-speed synchronous data transfer between the P89V51RB2/RC2/RD2
and peripheral devices or between several P89V51RB2/RC2/RD2 devices.
shows the correspondence between master and slave SPI devices. The SPICLK pin is the
SADDR = 1100 0000
--------------------------------------------------- -
SADDR = 1110 0000
--------------------------------------------------- -
SADDR = 1100 0000
--------------------------------------------------- -
SADEN = 1111 1001
SADEN = 1111 1010
SADEN = 1111 1100
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Given = 1100 0XX0
Given = 1110 0X0X
Given = 1100 00XX
Master or slave operation
10 MHz bit frequency (max)
LSB first or MSB first data transfer
Four programmable bit rates
End of transmission (SPIF)
Write collision flag protection (WCOL)
Wake-up from Idle mode (slave mode only)
Rev. 05 — 12 November 2009
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
© NXP B.V. 2009. All rights reserved.
Figure 17
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