P89V51RC2FN,112 NXP Semiconductors, P89V51RC2FN,112 Datasheet - Page 44

• Manufacturer Part Number: P89V51RC2FN,112
• Description: IC 80C51 MCU FLASH 32K 40-DIP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V51RC2FN,112

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1017 - BOARD 44-ZIF PLCC SOCKET622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2430-5; 935278782112; P89V51RC2FN

NXP Semiconductors
P89V51RB2_RC2_RD2_5
Product data sheet
Fig 18. SPI transfer format with CPHA = 0
SPICLK (CPOL = 0)
SPICLK (CPOL = 1)
SPICLK cycle #
(for reference)
(from master)
SS (to slave)
Table 29.
Table 30.
Table 31.
Bit addressable; Reset source(s): any reset; Reset value: 0000 0000B
Table 32.
(from slave)
Bit
2
1
0
SPR1
0
0
1
1
Bit
7
6
5 to 0
Bit
Symbol
MOSI
MISO
SPCR - SPI control register (address D5H) bit description
SPCR - SPI control register (address D5H) clock rate selection
SPSR - SPI status register (address AAH) bit allocation
SPSR - SPI status register (address AAH) bit description
Symbol
CPHA
SPR1
SPR0
Symbol
SPIF
WCOL
-
SPIF
7
MSB
MSB
1
Rev. 05 — 12 November 2009
WCOL
SPR0
0
1
0
1
2
6
6
6
Description
Clock Phase control bit. 1 = shift triggered on the trailing edge of the
clock; 0 = shift triggered on the leading edge of the clock.
SPI Clock Rate Select bit 1. Along with SPR0 controls the SPICLK
rate of the device when a master. SPR1 and SPR0 have no effect on
the slave. See
SPI Clock Rate Select bit 0. Along with SPR1 controls the SPICLK
rate of the device when a master. SPR1 and SPR0 have no effect on
the slave. See
Description
SPI interrupt flag. Upon completion of data transfer, this bit is set to ‘1’.
If SPIE = 1 and ES = 1, an interrupt is then generated. This bit is
cleared by software.
Write Collision Flag. Set if the SPI data register is written to during
data transfer. This bit is cleared by software.
Reserved for future use. Should be set to ‘0’ by user programs.
3
5
5
5
-
4
4
4
Table 30
Table 30
5
3
3
P89V51RB2/RC2/RD2
4
-
SPICLK = f
4
16
64
128
below.
below.
6
2
2
8-bit microcontrollers with 80C51 core
7
1
1
3
-
osc
LSB
LSB
8
divided by
2
-
002aaa529
…continued
© NXP B.V. 2009. All rights reserved.
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