P89V51RC2FN,112 NXP Semiconductors, P89V51RC2FN,112 Datasheet - Page 69

• Manufacturer Part Number: P89V51RC2FN,112
• Description: IC 80C51 MCU FLASH 32K 40-DIP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V51RC2FN,112

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1017 - BOARD 44-ZIF PLCC SOCKET622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2430-5; 935278782112; P89V51RC2FN

NXP Semiconductors
Table 66.
P89V51RB2_RC2_RD2_5
Product data sheet
Symbol Parameter
f
T
t
t
t
t
t
t
t
t
t
t
t
t
SPI
SPILEAD
SPILAG
SPICLKH
SPICLKL
SPIDSU
SPIDH
SPIA
SPIDIS
SPIDV
SPIOH
SPIR
SPIF
Fig 35. Shift register mode timing waveforms
SPICYC
SPI operating frequency
SPI cycle time
SPI enable lead time
SPI enable lag time
SPICLK HIGH time
SPICLK LOW time
SPI data set-up time
SPI data hold time
SPI access time
SPI disable time
SPI enable to output
data valid time
SPI output data hold
time
SPI rise time
SPI fall time
write to SBUF
output data
SPI interface timing
instruction
SPI outputs (SPICLK,
MOSI, MISO)
SPI inputs (SPICLK,
MOSI, MISO, SS)
SPI outputs (SPICLK,
MOSI, MISO)
SPI inputs (SPICLK,
MOSI, MISO, SS)
input data
clear RI
clock
ALE
t
t
QVXH
XHDV
valid
T
0
XLXL
Conditions
see
see
see
see
see
master or slave; see
Figure
master or slave; see
Figure
see
see
see
see
see
see
t
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
XHDX
36, 37, 38,
36, 37, 38,
t
valid
XHQX
1
Rev. 05 — 12 November 2009
36, 37, 38,
38,
38,
36, 37, 38,
36, 37, 38,
38,
38,
36, 37, 38,
36, 37, 38,
36, 37, 38,
36, 37, 38,
39
39
39
39
valid
2
39
39
39
39
39
39
39
39
39
valid
3
4T
2T
2T
Min
250
250
100
100
P89V51RB2/RC2/RD2
valid
cy(clk)
cy(clk)
cy(clk)
0
0
0
0
-
-
-
-
-
4
Variable clock
8-bit microcontrollers with 80C51 core
valid
5
T
cy(clk)
2000
2000
Max
160
111
100
100
80
-
-
-
-
-
-
-
-
/ 4
valid
6
f
osc
Min
222
250
250
111
111
100
100
valid
© NXP B.V. 2009. All rights reserved.
set TI
0
0
0
set RI
-
-
-
-
-
-
7
002aaa552
= 18 MHz
2000
2000
Max
160
111
100
100
80
10
-
-
-
-
-
-
-
-
69 of 80
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns