MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 100

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
All bits in the ECLKDIV register are readable while bits 6-0 are write once and bit 7 is not writable.
3.3.2.2
This register is reserved for factory testing and is not accessible to the user.
All bits read 0 and are not writable.
3.3.2.3
This register is reserved for factory testing and is not accessible to the user.
100
EDIV[5:0]
EDIVLD
PRDIV8
Reset
Reset
Reset
Field
5:0
7
6
W
W
W
R
R
R
EDIVLD
Clock Divider Loaded
0 Register has not been written.
1 Register has been written to since the last reset.
Enable Prescaler by 8
0 The oscillator clock is directly fed into the ECLKDIV divider.
1 The oscillator clock is divided by 8 before feeding into the clock divider.
Clock Divider Bits — The combination of PRDIV8 and EDIV[5:0] must divide the oscillator clock down to a
frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Please refer to
ECLKDIV Register”
RESERVED1
RESERVED2
7
0
7
0
0
7
0
0
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
PRDIV8
Figure 3-4. EEPROM Clock Divider Register (ECLKDIV)
6
0
6
0
0
6
0
0
for more information.
Table 3-3. ECLKDIV Field Descriptions
EDIV5
MC9S12HZ256 Data Sheet, Rev. 2.05
5
0
5
0
0
5
0
0
Figure 3-5. RESERVED1
Figure 3-6. RESERVED2
EDIV4
4
0
4
0
0
4
0
0
Description
EDIV3
3
0
3
0
0
3
0
0
EDIV2
2
0
2
0
0
2
0
0
Section 3.4.1.1, “Writing the
Freescale Semiconductor
EDIV1
1
0
1
0
0
1
0
0
EDIV0
0
0
0
0
0
0
0
0