MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 182

IC MCU 16BIT 2K FLASH 112-LQFP

MC9S12HZ128VAL

Manufacturer Part Number
MC9S12HZ128VAL
Description
IC MCU 16BIT 2K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12HZ128VAL

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, I²C, SCI, SPI
Peripherals
LCD, Motor control PWM, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
112-LQFP
Processor Series
S12H
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
6 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
85
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12HZ128VAL
Manufacturer:
Freescale Semiconductor
Quantity:
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Part Number:
MC9S12HZ128VAL
Manufacturer:
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Quantity:
20 000
Chapter 5 Clocks and Reset Generator (CRGV4)
5.3.2.12
This register is used to restart the COP time-out period.
Read: always reads 0x0000
Write: anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
5.4
This section gives detailed informations on the internal operation of the design.
5.4.1
The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased
flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers
a finer multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,...
126,128 based on the SYNR register.
The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on
the difference between the output frequency and the target frequency. The PLL can change between
acquisition and tracking modes either automatically or manually.
182
Reset
W
R
Writing any value other than 0x0055 or 0x00AA causes a COP reset. To restart the COP time-out
period you must write 0x0055 followed by a write of 0x00AA. Other instructions may be executed
between these writes but the sequence (0x0055, 0x00AA) must be completed prior to COP end of
time-out period to avoid a COP reset. Sequences of 0x0055 writes or sequences of 0x00AA writes
are allowed. When the WCOP bit is set, 0x0055 and 0x00AA writes must be done in the last 25%
of the selected time-out period; writing any value in the first 75% of the selected period will cause
a COP reset.
Functional Description
Phase Locked Loop (PLL)
Bit 7
CRG COP Timer Arm/Reset Register (ARMCOP)
0
0
7
Although it is possible to set the two dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
If (PLLSEL = 1), Bus Clock = PLLCLK / 2
Bit 6
0
0
6
PLLCLK
Figure 5-15. ARMCOP Register Diagram
MC9S12HZ256 Data Sheet, Rev. 2.05
Bit 5
0
0
5
=
2 OSCCLK
CAUTION
Bit 4
0
0
4
---------------------------------- -
REFDV
SYNR
Bit 3
0
0
3
+
+
1
1
Bit 2
0
0
2
Freescale Semiconductor
Bit 1
0
0
1
Bit 0
0
0
0

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