MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 504

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 17 Dual Output Voltage Regulator (VREG3V3V2)
17.2.3
Signals V
These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R
ceramic).
In Shutdown Mode an external supply at V
17.2.4
Signals V
PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors
(100 nF...220 nF, X7R ceramic).
In Shutdown Mode an external supply at V
17.2.5
This optional signal is used to shutdown VREG3V3. In that case V
provided externally. Shutdown Mode is entered with V
VREG3V3 is either in Full Performance Mode or in Reduced Power Mode.
For the connectivity of V
17.3
This subsection provides a detailed description of all registers accessible in VREG3V3.
17.3.1
Figure 17-2
504
DD
DDPLL
Memory Map and Register Definition
Address
0x0000
Offset
V
V
V
Module Memory Map
provides an overview of all used registers.
/V
DD
DDPLL
REGEN
Switching from FPM or RPM to shutdown of VREG3V3 and vice versa is
not supported while the MCU is powered.
SS
/V
, V
are the primary outputs of VREG3V3 that provide the power supply for the core logic.
SSPLL
SS
, V
— Optional Regulator Enable
— Regulator Output1 (Core Logic)
are the secondary outputs of VREG3V3 that provide the power supply for the
SSPLL
REGEN
see device overview chapter.
— Regulator Output2 (PLL)
VREG3V3 Control Register (VREGCTRL)
Table 17-2. VREG3V3 Memory Map
MC9S12HZ256 Data Sheet, Rev. 2.05
DD
DDPLL
/V
SS
NOTE
/V
Use
can replace the voltage regulator.
SSPLL
REGEN
can replace the voltage regulator.
being low. If V
DD
/V
SS
and V
REGEN
DDPLL
Freescale Semiconductor
is high, the
/V
Access
R/W
SSPLL
must be