MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 68

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.3.2.5
The banked FPROT register defines which Flash sectors are protected against program or erase operations.
All bits in the FPROT register are readable and writable with restrictions except for RNV[6] which is only
readable (see
During reset, the banked FPROT registers are loaded from the Flash Configuration Field at the address
shown in
upper sector of the Flash memory must be unprotected, then the Flash Protect/Security byte located as
described in
68
KEYACC
BKSEL
CBEIE
Reset
Field
CCIE
7
6
5
0
W
R
Table
FPOPEN
Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command
buffer in the Flash module.
0 Command buffer empty interrupt disabled.
1 An interrupt will be requested whenever the CBEIF flag (see
Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been
completed in the Flash module.
0 Command complete interrupt disabled.
1 An interrupt will be requested whenever the CCIF flag (see
Enable Security Key Writing
0 Flash writes are interpreted as the start of a command write sequence.
1 Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array return invalid
Block Select — The BKSEL bit indicates which register bank is active.
0 Select register bank associated with Flash block 0.
1 Select register bank associated with Flash block 1.
Table 2-1
Flash Protection Register (FPROT)
Section 2.3.2.6, “Flash Protection
F
7
is set.
is set.
data.
2-10. To change the Flash protection that will be loaded during the reset sequence, the
= Unimplemented or Reserved
must be reprogrammed.
RNV6
6
F
Figure 2-8. Flash Protection Register (FPROT)
Table 2-9. FCNFG Field Descriptions
Table 2-10. Reset Loading of FPROT
FPHDIS
Flash Address
MC9S12HZ256 Data Sheet, Rev. 2.05
5
F
0xFF0D
0xFF0C
Restrictions”).
4
F
Protection Byte for
Description
FPHS
Flash Block 0
Flash Block 1
F
3
Section 2.3.2.7, “Flash Status Register
Section 2.3.2.7, “Flash Status Register (FSTAT)”)
FPLDIS
2
F
Freescale Semiconductor
1
F
FPLS
(FSTAT)”)
F
0