STM8S103F3P6 STMicroelectronics, STM8S103F3P6 Datasheet - Page 106

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STM8S103F3P6

Manufacturer Part Number
STM8S103F3P6
Description
MCU 8BIT 8KB FLASH 20-TSSOP
Manufacturer
STMicroelectronics
Series
STM8Sr
Datasheet

Specifications of STM8S103F3P6

Core Processor
STM8
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
640 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.95 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
STM8S10x
Core
STM8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
16
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWSTM8
Development Tools By Supplier
STM8/128-MCKIT, STM8S-DISCOVERY, ST-LINK, STICE-SYS001, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Featured Product
STM32 Cortex-M3 Companion Products
For Use With
497-10593 - KIT STARTER FOR STM8S207/8 SER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Ordering information
106/113
OPT3 watchdog
OPT4 wakeup
OPT5 crystal oscillator stabilization HSECNT (check only one option)
[ ] 2048 HSE cycles
[ ] 128 HSE cycles
[ ] 8 HSE cycles
[ ] 0.5 HSE cycles
OPT6 is reserved
WWDG_HALT
(check only one option)
WWDG_HW
(check only one option)
IWDG_HW
(check only one option)
LSI_EN
(check only one option)
HSITRIM
(check only one option)
PRSC
(check only one option)
CKAWUSEL
(check only one option)
EXTCLK
(check only one option)
Comments:
Supply operating range
in the application:
Notes:
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DocID15441 Rev 6
[ ] for 16 MHz to 128 kHz prescaler
[ ] for 8 MHz to 128 kHz prescaler
[ ] for 4 MHz to 128 kHz prescaler
[ ] LSI clock source selected for AWU
[ ] HSE clock with prescaler selected as clock source for
for AWU
[ ] External crystal connected to OSCIN/OSCOUT
[ ] External clock signal on OSCIN
[ ] 0: No reset generated on halt if WWDG active
[ ] 1: Reset generated on halt if WWDG active
[ ] 0: WWDG activated by software
[ ] 1: WWDG activated by hardware
[ ] 0: IWDG activated by software
[ ] 1: IWDG activated by hardware
[ ] 0: LSI clock is not available as CPU clock source
[ ] 1: LSI clock is available as CPU clock source
[ ] 0: 3-bit trimming supported in CLK_HSITRIMR register
[ ] 1: 4-bit trimming supported in CLK_HSITRIMR register
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