STM8S103F3P6 STMicroelectronics, STM8S103F3P6 Datasheet - Page 42

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STM8S103F3P6

Manufacturer Part Number
STM8S103F3P6
Description
MCU 8BIT 8KB FLASH 20-TSSOP
Manufacturer
STMicroelectronics
Series
STM8Sr
Datasheet

Specifications of STM8S103F3P6

Core Processor
STM8
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
640 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.95 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
STM8S10x
Core
STM8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
16
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWSTM8
Development Tools By Supplier
STM8/128-MCKIT, STM8S-DISCOVERY, ST-LINK, STICE-SYS001, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Featured Product
STM32 Cortex-M3 Companion Products
For Use With
497-10593 - KIT STARTER FOR STM8S207/8 SER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Option bytes
8
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Addr.
Option
Option
Option bits
name
byte no.
7
0x4800
Read-out
OPT0
ROP [7:0]
protection
(ROP)
0x4801
User boot
OPT1
UBC [7:0]
code(UBC)
0x4802
NOPT1
NUBC [7:0]
0x4803
Alternate
OPT2
AFR7
function
0x4804
NOPT2
NAFR7
remapping
(AFR)
0x4805h
Miscell.
OPT3
Reserved
option
0x4806
NOPT3
Reserved
0x4807
Clock
OPT4
Reserved
option
0x4808
NOPT4
Reserved
0x4809
HSE clock
OPT5
HSECNT [7:0]
startup
0x480A
NOPT5
NHSECNT [7:0]
Option byte no.
OPT0
42/113
STM8S103K3 STM8S103F3 STM8S103F2
Table 11: Option bytes
6
5
4
3
AFR5
AFR4
AFR3
AFR6
NAFR6
NAFR5
NAFR4
NAFR3
HSI
LSI_ EN
TRIM
NHSI
NLSI_
TRIM
EN
EXT CLK
NEXT
CLK
Table 12: Option byte description
Description
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
DocID15441 Rev 6
Factory
default
setting
2
1
0
00h
00h
FFh
AFR2
AFR1
AFR0
00h
NAFR2
NAFR1
NAFR0
FFh
IWDG
WWDG
WWDG
00h
_HW
_HW
_HALT
NIWDG
NWWDG
NWW
FFh
_HW
_HW
G_HALT
CKAWU
PRS C1
PRS C0
00h
SEL
NCKA
NPRSC1
NPR
FFh
WUSEL
SC0
00h
FFh

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