STM8S103F3P6

Manufacturer Part NumberSTM8S103F3P6
DescriptionMCU 8BIT 8KB FLASH 20-TSSOP
ManufacturerSTMicroelectronics
SeriesSTM8S
STM8S103F3P6 datasheet
 


Specifications of STM8S103F3P6

Core ProcessorSTM8Core Size8-Bit
Speed16MHzConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o16
Program Memory Size8KB (8K x 8)Program Memory TypeFLASH
Eeprom Size640 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.95 V ~ 5.5 VData ConvertersA/D 5x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-TSSOPProcessor SeriesSTM8S10x
CoreSTM8Data Bus Width8 bit
Data Ram Size1 KBInterface TypeI2C, SPI, UART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os16
Number Of Timers7Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWSTM8
Development Tools By SupplierSTM8/128-MCKIT, STM8S-DISCOVERY, ST-LINK, STICE-SYS001, STX-RLINKMinimum Operating Temperature- 40 C
On-chip Adc10 bit, 5 ChannelFeatured ProductSTM32 Cortex-M3 Companion Products
For Use With497-10593 - KIT STARTER FOR STM8S207/8 SERLead Free Status / RoHS StatusLead free / RoHS Compliant
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Page 52/113

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Electrical characteristics
(2)
To calculate P
(T
), use the formula P
Dmax
A
value for T
given in the previous table and the value for Θ
Jmax
(3)
Τ
is given by the test limit. Above this value the product behavior is not guaranteed.
Jmax
Functionality
not
guaranteed
in this area
Table 20: Operating conditions at power-up/power-down
Symbol
Parameter
V
rise time rate
DD
t
VDD
V
fall time rate
DD
t
Reset release delay
TEMP
V
Power-on reset threshold
IT+
V
Brown-out reset threshold
IT-
V
Brown-out reset hysteresis
HYS(BOR)
(1)
Reset is always generated after a t
minimum ooperating voltage (V
10.3.1
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor C
V
pin. C
is specified in the Operating conditions section. Care should be taken to limit
CAP
EXT
the series inductance to less than 15 nH.
52/113
=(T
- T
)/Θ
Dmax
Jmax
A
Figure 9: f
CPUmax
f
CPU (MHz)
16
12
Functionality guaranteed
@T A -40 to 125 °C
8
4
0
4.0
2.95
Conditions
(1)
V
rising
DD
delay. The application must ensure that V
TEMP
min) when the t
delay has elapsed.
DD
TEMP
DocID15441 Rev 6
STM8S103K3 STM8S103F3 STM8S103F2
(see
Thermal characteristics
JA
given in
Thermal
characteristics.
JA
versus V
DD
5.0
5.5
Supply voltage
Min
Typ
Max
2
2
1.7
2.6
2.7
2.85
2.5
2.65
2.8
70
is still above the
DD
) with the
Unit
μs/V
ms
V
mV
to the
EXT