STM8S103F3P6

Manufacturer Part NumberSTM8S103F3P6
DescriptionMCU 8BIT 8KB FLASH 20-TSSOP
ManufacturerSTMicroelectronics
SeriesSTM8S
STM8S103F3P6 datasheet
 


Specifications of STM8S103F3P6

Core ProcessorSTM8Core Size8-Bit
Speed16MHzConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o16
Program Memory Size8KB (8K x 8)Program Memory TypeFLASH
Eeprom Size640 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.95 V ~ 5.5 VData ConvertersA/D 5x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-TSSOPProcessor SeriesSTM8S10x
CoreSTM8Data Bus Width8 bit
Data Ram Size1 KBInterface TypeI2C, SPI, UART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os16
Number Of Timers7Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWSTM8
Development Tools By SupplierSTM8/128-MCKIT, STM8S-DISCOVERY, ST-LINK, STICE-SYS001, STX-RLINKMinimum Operating Temperature- 40 C
On-chip Adc10 bit, 5 ChannelFeatured ProductSTM32 Cortex-M3 Companion Products
For Use With497-10593 - KIT STARTER FOR STM8S207/8 SERLead Free Status / RoHS StatusLead free / RoHS Compliant
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List of figures
List of figures
Figure 1. Block diagram .........................................................................................................................10
Figure 2. Flash memory organization ....................................................................................................13
Figure 3. STM8S103Kx UFQFPN32/LQFP32 pinout .............................................................................19
Figure 4. STM8S103Fx TSSOP20/SO20 pinout ....................................................................................22
Figure 5. STM8S103Fx UFQFPN20-pin pinout .....................................................................................23
Figure 6. Memory map ...........................................................................................................................26
Figure 7. Pin loading conditions .............................................................................................................48
Figure 8. Pin input voltage .....................................................................................................................49
Figure 9. f
versus V
CPUmax
DD
Figure 10. External capacitor C
Figure 11. Typ I
vs. V
DD(RUN)
DD
Figure 12. Typ I
vs. f
DD(RUN)
CPU
Figure 13. Typ I
vs. V
DD(RUN)
DD
Figure 14. Typ I
vs. V
DD(WFI)
DD
Figure 15. Typ I
vs. f
DD(WFI)
CPU
Figure 16. Typ I
vs. V
DD(WFI)
DD
Figure 17. HSE external clocksource .....................................................................................................64
Figure 18. HSE oscillator circuit diagram ...............................................................................................65
Figure 19. Typical HSI accuracy at V
Figure 20. Typical HSI frequency variation vs V
Figure 21. Typical LSI frequency variation vs V
Figure 22. Typical V
and V
IL
IH
Figure 23. Typical pull-up resistance vs V
Figure 24. Typical pull-up current vs V
Figure 25. Typ. V
@ V
= 5 V (standard ports) ................................................................................72
OL
DD
Figure 26. Typ. V
@ V
= 3.3 V (standard ports) .............................................................................73
OL
DD
Figure 27. Typ. V
@ V
= 5 V (true open drain ports) ......................................................................73
OL
DD
Figure 28. Typ. V
@ V
= 3.3 V (true open drain ports) ...................................................................74
OL
DD
Figure 29. Typ. V
@ V
= 5 V (high sink ports) ................................................................................74
OL
DD
Figure 30. Typ. V
@ V
= 3.3 V (high sink ports) .............................................................................75
OL
DD
Figure 31. Typ. V
- V
@ V
DD
OH
Figure 32. Typ. V
- V
@ V
DD
OH
Figure 33. Typ. V
- V
@ V
DD
OH
Figure 34. Typ. V
- V
@ V
DD
OH
Figure 35. Typical NRST V
and V
IL
Figure 36. Typical NRST pull-up resistance vs V
Figure 37. Typical NRST pull-up current vs V
Figure 38. Recommended reset pin protection ......................................................................................79
Figure 39. SPI timing diagram - slave mode and CPHA = 0 ..................................................................81
Figure 40. SPI timing diagram - slave mode and CPHA = 1 ..................................................................81
Figure 41. SPI timing diagram - master mode
Figure 42. Typical application with I
Figure 43. ADC accuracy characteristics ...............................................................................................86
Figure 44. Typical application with ADC ................................................................................................87
Figure 45. 32-pin low profile quad flat package (7 x 7) ..........................................................................91
Figure 46. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ............................................93
Figure 47. 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) ................................94
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.......................................................................................................53
EXT
HSE user external clock, f
CPU
HSE user external clock, V
DD
HSI RC osc, f
= 16 MHz .................................................................62
CPU
HSE user external clock, f
CPU
HSE user external clock, V
DD
HSI RC osc, f
= 16 MHz .................................................................63
CPU
= 5 V vs 5 temperatures ..........................................................66
DD
@ 4 temperatures ..................................................67
DD
@ 4 temperatures ...................................................67
DD
vs V
@ 4 temperatures ......................................................................70
DD
@ 4 temperatures ............................................................70
DD
@ 4 temperatures .................................................................71
DD
= 5 V (standard ports) .......................................................................75
DD
= 3.3 V (standard ports) ...................................................................76
DD
= 5 V (high sink ports) .......................................................................76
DD
= 3.3 V (high sink ports) ....................................................................77
DD
vs V
@ 4 temperatures ...........................................................78
IH
DD
@ 4 temperatures .................................................78
DD
@ 4 temperatures ......................................................79
DD
(1)
...................................................................................82
2
C bus and timing diagram ............................................................86
DocID15441 Rev 6
STM8S103K3 STM8S103F3 STM8S103F2
= 16 MHz .............................................61
= 5 V ....................................................61
= 16 MHz ..............................................62
= 5 V .....................................................63