STM8S103F3P6

Manufacturer Part NumberSTM8S103F3P6
DescriptionMCU 8BIT 8KB FLASH 20-TSSOP
ManufacturerSTMicroelectronics
SeriesSTM8S
STM8S103F3P6 datasheet
 


Specifications of STM8S103F3P6

Core ProcessorSTM8Core Size8-Bit
Speed16MHzConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o16
Program Memory Size8KB (8K x 8)Program Memory TypeFLASH
Eeprom Size640 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.95 V ~ 5.5 VData ConvertersA/D 5x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-TSSOPProcessor SeriesSTM8S10x
CoreSTM8Data Bus Width8 bit
Data Ram Size1 KBInterface TypeI2C, SPI, UART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os16
Number Of Timers7Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWSTM8
Development Tools By SupplierSTM8/128-MCKIT, STM8S-DISCOVERY, ST-LINK, STICE-SYS001, STX-RLINKMinimum Operating Temperature- 40 C
On-chip Adc10 bit, 5 ChannelFeatured ProductSTM32 Cortex-M3 Companion Products
For Use With497-10593 - KIT STARTER FOR STM8S207/8 SERLead Free Status / RoHS StatusLead free / RoHS Compliant
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STM8S103K3 STM8S103F3 STM8S103F2
Symbol
Parameter
t
STOP condition setup time
su(STO)
t
STOP to START condition time
w(STO:ST A)
(bus free)
C
Capacitive load for each bus line
b
(1)
f
, must be at least 8 MHz to achieve max fast I
MASTER
(2)
2
Data based on standard I
(3)
The maximum hold time of the start condition has only to be met if the interface does not stretch the
low time
(4)
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL
Figure 42: Typical application with I
2
I
C bus
SDA
t
f(SDA)
SCL
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD.
10.3.10
10-bit ADC characteristics
Subject to general operating conditions for V
Standard mode I
(2)
Min
4.0
4.7
2
C speed (400kHz)
C protocol requirement, not tested in production
V DD
V DD
4.7k
4.7k
100
SDA
100
SCL
START
t
r(SDA)
t
t
su(SDA)
h(SDA)
t
t
t
t
t
h(STA)
w(SCLH)
w(SCLL)
r(SCL)
f(SCL)
, f
DD
DocID15441 Rev 6
Electrical characteristics
2
2
C
Fast mode I
C
(2)
(2)
(2)
Max
Min
Max
0.6
1.3
400
400
2
C bus and timing diagram
STM8S
REPEATED
START
t
t
su(STA)
w(STO:STA)
START
STOP
t
su(STO)
ai17490
, and T
unless otherwise specified.
MASTER
A
Unit
(1)
μs
pF
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