STM8S103F3P6

Manufacturer Part NumberSTM8S103F3P6
DescriptionMCU 8BIT 8KB FLASH 20-TSSOP
ManufacturerSTMicroelectronics
SeriesSTM8S
STM8S103F3P6 datasheet
 


Specifications of STM8S103F3P6

Core ProcessorSTM8Core Size8-Bit
Speed16MHzConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o16
Program Memory Size8KB (8K x 8)Program Memory TypeFLASH
Eeprom Size640 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.95 V ~ 5.5 VData ConvertersA/D 5x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-TSSOPProcessor SeriesSTM8S10x
CoreSTM8Data Bus Width8 bit
Data Ram Size1 KBInterface TypeI2C, SPI, UART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os16
Number Of Timers7Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWSTM8
Development Tools By SupplierSTM8/128-MCKIT, STM8S-DISCOVERY, ST-LINK, STICE-SYS001, STX-RLINKMinimum Operating Temperature- 40 C
On-chip Adc10 bit, 5 ChannelFeatured ProductSTM32 Cortex-M3 Companion Products
For Use With497-10593 - KIT STARTER FOR STM8S207/8 SERLead Free Status / RoHS StatusLead free / RoHS Compliant
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STM8S103K3 STM8S103F3 STM8S103F2
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Data
EEPROM
memory
Low density
Flash program
memory
 
(8 Kbytes)
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated,
any attempt to toggle its status triggers a global erase of the program and data memory. Even
if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
4.5
Clock controller
The clock controller distributes the system clock (f
to the core and the peripherals. It also manages clock gating for low power modes and ensures
clock robustness.
Features
Clock prescaler: To get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock source
is ready. The design guarantees glitch-free switching.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock sources: Four different clock sources can be used to drive the master
clock:
-
1-16 MHz high-speed external crystal (HSE)
Figure 2: Flash memory organization
Data memory area ( 640 bytes)
Option bytes
UBC area
Remains write protected during IAP
Program memory area
Write access possible for IAP
MASTER
DocID15441 Rev 6
Product overview
Programmable
area from 64
bytes(1 page)
up to 8 Kbytes
(in 1 page steps)
) coming from different oscillators
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