STM8S103F3P6

Manufacturer Part NumberSTM8S103F3P6
DescriptionMCU 8BIT 8KB FLASH 20-TSSOP
ManufacturerSTMicroelectronics
SeriesSTM8S
STM8S103F3P6 datasheet
 


Specifications of STM8S103F3P6

Core ProcessorSTM8Core Size8-Bit
Speed16MHzConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o16
Program Memory Size8KB (8K x 8)Program Memory TypeFLASH
Eeprom Size640 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.95 V ~ 5.5 VData ConvertersA/D 5x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-TSSOPProcessor SeriesSTM8S10x
CoreSTM8Data Bus Width8 bit
Data Ram Size1 KBInterface TypeI2C, SPI, UART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os16
Number Of Timers7Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWSTM8
Development Tools By SupplierSTM8/128-MCKIT, STM8S-DISCOVERY, ST-LINK, STICE-SYS001, STX-RLINKMinimum Operating Temperature- 40 C
On-chip Adc10 bit, 5 ChannelFeatured ProductSTM32 Cortex-M3 Companion Products
For Use With497-10593 - KIT STARTER FOR STM8S207/8 SERLead Free Status / RoHS StatusLead free / RoHS Compliant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Page 51
52
Page 52
53
Page 53
54
Page 54
55
Page 55
56
Page 56
57
Page 57
58
Page 58
59
Page 59
60
Page 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
Page 59/113

Download datasheet (2Mb)Embed
PrevNext
STM8S103K3 STM8S103F3 STM8S103F2
Symbol
Parameter
Wakeup time active
halt mode to run
(3)
mode
Wakeup time active
halt mode to run
(3)
mode
Wakeup time from
halt mode to run
t
WU(H)
(3)
mode
(1)
Data guaranteed by design, not tested in production.
(2)
t
= 2 x 1/f
+ 6 x 1/f
WU(WFI)
master
(3)
Measured from interrupt event to interrupt vector fetch.
(4)
Configured by the REGAH bit in the CLK_ICKR register.
(5)
Configured by the AHALT bit in the FLASH_CR1 register.
(6)
Plus 1 LSI clock depending on synchronization.
10.3.2.6
Total current consumption and timing in forced reset state
Table 30: Total current consumption and timing in forced reset state
Symbol
Parameter
I
Supply current in reset
DD(R)
(2)
state
t
Reset pin release to
RESETBL
vector fetch
(1)
Data guaranteed by design, not tested in production.
(2)
Characterized with all I/Os tied to V
10.3.2.7
Current consumption of on-chip peripherals
Subject to general operating conditions for V
Conditions
MVR voltage
Flash in operating
regulator
(5)
mode
(4)
off
MVR voltage
Flash in
regulator
power-down
(4)
(5)
off
mode
(5)
Flash in operating mode
(5)
Flash in power-down mode
CPU.
Conditions
V
= 5 V
DD
V
= 3.3 V
DD
.
SS
and T
DD
DocID15441 Rev 6
Electrical characteristics
(1)
Typ
Unit
Max
HSI
(6)
(after
48
wakeup)
HSI
(6)
(after
50
wakeup)
52
54
Typ
(1)
Max
400
300
150
.
A
Unit
μA
μs
59/113