MC908GR16VFAE Freescale Semiconductor, MC908GR16VFAE Datasheet - Page 132

• Manufacturer Part Number: MC908GR16VFAE
• Description: IC MCU 16K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR16VFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Input/Output Ports (PORTS)
When bit DDRDx is a 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a 0,
reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
12.5.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each
of the eight port D pins. Each bit is individually configurable and requires that the data direction register,
DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRD is configured for output mode.
PTDPUE7–PTDPUE0 — Port D Input Pullup Enable Bits
132
1. X = Don’t care
2. I/O pin pulled up to V
3. Writing affects data register, but does not affect input.
4. Hi-Z = High imp[edance
PTDPUE
These writable bits are software programmable to enable pullup devices on an input port bit.
Bit
1
0
X
1 = Corresponding port D pin configured to have internal pullup
0 = Corresponding port D pin has internal pullup disconnected
Address:
DDRD
Reset:
Read:
Write:
Bit
0
0
1
Figure 12-16. Port D Input Pullup Enable Register (PTDPUE)
DD
PTDPUE7
$000F
Bit 7
by internal pullup device.
PTD
0
X
Bit
X
X
(1)
PTDPUE6
Input, Hi-Z
Input, V
6
0
Table 12-5. Port D Pin Functions
I/O Pin
Output
MC68HC908GR16 Data Sheet, Rev. 5.0
Mode
DD
PTDPUE5
(2)
(4)
5
0
Table 12-5
PTDPUE4
Accesses to DDRD
DDRD7–DDRD0
DDRD7–DDRD0
DDRD7–DDRD0
4
0
Read/Write
PTDPUE3
summarizes the operation of the port D pins.
3
0
PTDPUE2
2
0
PTD7–PTD0
Read
PTDPUE1
Pin
Pin
1
0
Accesses to PTD
Freescale Semiconductor
PTDPUE0
Bit 0
0
PTD7–PTD0
PTD7–PTD0
PTD7–PTD0
Write
(3)
(3)