MC908GR16VFAE Freescale Semiconductor, MC908GR16VFAE Datasheet - Page 59

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MC908GR16VFAE

Manufacturer Part Number
MC908GR16VFAE
Description
IC MCU 16K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheets

Specifications of MC908GR16VFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
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Chapter 4
Clock Generator Module (CGM)
4.1 Introduction
This section describes the clock generator module. The CGM generates the crystal clock signal,
CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock
signal, CGMOUT, which is based on either the crystal clock divided by two or the phase-locked loop (PLL)
clock, CGMVCLK, divided by two. In user mode, CGMOUT is the clock from which the SIM derives the
system clocks, including the bus clock, which is at a frequency of CGMOUT/2. In monitor mode, PTC3
determines the bus clock. The PLL is a fully functional frequency generator designed for use with crystals
or ceramic resonators. The PLL can generate an 8-MHz bus frequency using a 32-kHz crystal.
4.2 Features
Features of the CGM include:
4.3 Functional Description
The CGM consists of three major submodules:
Figure 4-1
Freescale Semiconductor
Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal
reference
Low-frequency crystal operation with low-power operation and high-output frequency resolution
Programmable prescaler for power-of-two increases in frequency
Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation
Automatic bandwidth control mode for low-jitter operation
Automatic frequency lock detector
CPU interrupt on entry or exit from locked condition
Configuration register bit to allow oscillator operation during stop mode
Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency
clock, CGMXCLK.
Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock,
CGMVCLK.
Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by
two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives
the system clocks from either CGMOUT or CGMXCLK.
shows the structure of the CGM.
MC68HC908GR16 Data Sheet, Rev. 5.0
59

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