MC908GR16VFAE Freescale Semiconductor, MC908GR16VFAE Datasheet - Page 245

• Manufacturer Part Number: MC908GR16VFAE
• Description: IC MCU 16K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR16VFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Enter monitor mode with pin configuration shown in
rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins
can change.
Once out of reset, the MCU waits for the host to send eight security bytes (see
19.3.2
indicating that it is ready to receive a command.
19.3.1.1 Normal Monitor Mode
Table 19-1
If V
of the input clock. If PTB4 is high with V
will be a divide-by-four of the input clock. Holding the PTB4 pin low when entering monitor mode causes
a bypass of a divide-by-two stage at the oscillator only if V
CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal
bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency.
When monitor mode was entered with V
as long as V
Freescale Semiconductor
2
3
5
1 μF
1 μF
TST
DB9
Security). After the security bytes, the MCU sends a break signal (10 consecutive 0s) to the host,
is applied to IRQ and PTB4 is low upon monitor mode entry, the bus frequency is a divide-by-two
+
+
7
8
1
3
4
5
shows the pin conditions for entering monitor mode.
TST
C1+
C1–
C2+
C2–
is applied to either IRQ or RST.
MAX232
Figure 19-12. Forced Monitor Mode Circuit (IRQ = GND)
GND
V
V+
V–
CC
16
15
2
10
6
9
V
DD
+
+
C5
C4
2
MC68HC908GR16 Data Sheet, Rev. 5.0
74HC125
1
TST
+
TST
3
C3
74HC125
applied to IRQ upon monitor mode entry, the bus frequency
on IRQ, the computer operating properly (COP) is disabled
6
4
33 pF
15 pF
5
Table 19-1
32.768 kHz
V
DD
10 kΩ
TST
10 k
is applied to IRQ. In this event, the
4.7 k
by pulling RST low and then high. The
N.C.
10 MΩ
RST
OSC2
OSC1
IRQ
PTA0
MC68HC908GR16
Monitor ROM (MON)
PTB4
PTB0
PTB1
PTA1
V
V
V
V
DDA
SSA
DD
SS
10 k
V
DD
N.C.
N.C.
N.C.
0.1 μF
245