MC908GR16VFAE Freescale Semiconductor, MC908GR16VFAE Datasheet - Page 137

• Manufacturer Part Number: MC908GR16VFAE
• Description: IC MCU 16K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR16VFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.2.3.4 Illegal Opcode Reset
An illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. An illegal
opcode reset sets the ILOP bit in the SIM reset status register.
If the stop enable bit, STOP, in the mask option register is a 0, the STOP instruction causes an illegal
opcode reset.
13.2.3.5 Illegal Address Reset
An illegal address reset is an internal reset caused by opcode fetch from an unmapped address. An illegal
address reset sets the ILAD bit in the SIM reset status register.
A data fetch from an unmapped address does not generate a reset.
13.2.4 System Integration Module (SIM) Reset Status Register
This read-only register contains flags to show reset sources. All flag bits are automatically cleared
following a read of the register. Reset service can read the SIM reset status register to clear the register
after power-on reset and to determine the source of any subsequent reset.
The register is initialized on power-up as shown with the POR bit set and all other bits cleared. During a
POR or any other internal reset, the RST pin is pulled low. After the pin is released, it will be sampled 32
CGMXCLK cycles later. If the pin is not above a V
in addition to whatever other bits are set.
POR — Power-On Reset Flag
PIN — External Reset Flag
COP — Computer Operating Properly Reset Bit
ILOP — Illegal Opcode Reset Bit
Freescale Semiconductor
1 = Power-on reset since last read of SRSR
0 = Read of SRSR since last power-on reset
1 = External reset via RST pin since last read of SRSR
0 = POR or read of SRSR since any reset
1 = Last reset caused by timeout of COP counter
0 = POR or read of SRSR since any reset
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR since any reset
Address:
Only a read of the SIM reset status register clears all reset flags. After
multiple resets from different sources without reading the register, multiple
flags remain set.
Read:
Write:
POR:
$FE01
POR
Bit 7
1
Figure 13-2. SIM Reset Status Register (SRSR)
= Unimplemented
PIN
6
0
MC68HC908GR16 Data Sheet, Rev. 5.0
COP
5
0
NOTE
IH
ILOP
at that time, then the PIN bit in the SRSR may be set
4
0
ILAD
3
0
MODRST
2
0
LVI
1
0
Bit 0
0
0
Resets
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