MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 103

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

out of internal SRAM or cache during DMA access.
The ColdFire processor or an external emulator using the debug module can perform these
initialization functions.
4.5.1 SRAM Initialization Code
The code segment below initializes the SRAM. The code sets the base address of the SRAM
at 0x2000_0000 and then initializes the RAM to zeros.
RAMBASE
RAMVALID
move.l
movec.l
The following loop initializes the entire SRAM to zero:
lea.l
move.l
SRAM_INIT_LOOP:
clr.l
subq.l
bne.b
The following function copies the number of bytesToMove from the source (*src) to the
processor’s local RAM at an offset relative to the SRAM base address defined by
destinationOffset. The bytesToMove must be a multiple of 16. For best performance, source
and destination SRAM addresses should be line-aligned (0-modulo-16).
; copyToCpuRam (*src, destinationOffset, bytesToMove)
RAMBASE
RAMFLAGS
; stack arguments and locations
; +0
; +4
; +8
; +12
; +16
; +20
; +24
lea.l
movem.l
move.l
movec.l
move.l
lea.l
add.l
saved d2
saved d3
saved d4
returnPc
pointer to source operand
destinationOffset
bytesToMove
EQU
EQU
#RAMBASE+RAMVALID,D0
D0, RAMBAR
RAMBASE,A0
#1024,D0
(A0)+
#1,D0
SRAM_INIT_LOOP
EQU
EQU
-12(a7),a7
#0x1c,(a7)
RAMBASE+RAMFLAGS,a0
a0,rambar
16(a7),a0
RAMBASE,a1
20(a7),a1
Freescale Semiconductor, Inc.
For More Information On This Product,
0x20000000
0x00000035
0x20000000
0x00000035
Chapter 4. Local Memory
Go to: www.freescale.com
;set this variable to 0x20000000
;load RAMBASE + valid bit into D0
;load RAMBAR and enable SRAM
;load pointer to SRAM
;load loop counter into D0
;clear 4 bytes of SRAM
;decrement loop counter
;exit if done; else continue looping
;SRAM base address
;RAMBAR valid + mask bits
;allocate temporary space
;store D2/D3/D4 registers
;define RAMBAR contents
;load it
;load argument defining *src
;memory pointer to RAM base
;include destinationOffset
SRAM Initialization
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