MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 268

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SDRAM Example
The associated CBM bits should also be initialized. After DACR[IMRS] is set, the next
access to the SDRAM address space generates the
address of the access should be selected to place the correct mode information on the
SDRAM address pins. The address is not multiplexed for the
access can be a read or write. The important thing is that the address output of that access
needs the correct mode programming information on the correct address bits.
Figure 11-24 shows the
11.5 SDRAM Example
This example interfaces a 2M x 32-bit x 4 bank SDRAM component to a MCF5307
operating at 40 MHz. Table 11-32 lists design specifications for this example.
11-34
Speed grade (-8E)
10 rows, 8 columns
Two bank-select lines to access four internal banks
ACTV
Period between auto refresh and
ACTV
Precharge command to
Last data input to
Auto refresh period for 4096 rows (t
-to-read/write delay (t
command to precharge command (t
Figure 11-24. Mode Register Set (
Table 11-32. SDRAM Example Specifications
SRAS, SCAS
Freescale Semiconductor, Inc.
RAS[1] or [0]
MRS
PALL
For More Information On This Product,
DRAMW
BCLKO
A[31:0]
D[31:0]
command, which occurs in the first clock of the bus cycle.
command (t
Parameter
ACTV
RCD
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command (t
)
MCF5307 User’s Manual
ACTV
RWL
REF
MRS
command (t
)
)
RAS
RP
)
)
RC
)
MRS
MRS
command to that SDRAM. The
40 MHz (25-nS period)
20 nS (min.)
70 nS
48 nS (min.)
20 nS (min.)
1 bus clock (25 nS)
64 mS
) Command
Specification
MRS
command. The
MRS