MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 144

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

28–22
12–6
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20–18/
4–2
20/4
19/3
18/2
17/1
16/0
Bits
Background Debug Mode (BDM)
5.5 Background Debug Mode (BDM)
The ColdFire Family implements a low-level system debugger in the microprocessor
hardware. Communication with the development system is handled through a dedicated,
high-speed serial command interface. The ColdFire architecture implements the BDM
controller in a dedicated hardware module. Although some BDM operations, such as CPU
register accesses, require the CPU to be halted, other BDM commands, such as memory
accesses, can be executed while the processor is running.
5.5.1 CPU Halt
Although many BDM operations can occur in parallel with CPU operations, unrestricted
BDM operation requires the CPU to be halted. The sources that can cause the CPU to halt
are listed below in order of priority:
5-16
1. A catastrophic fault-on-fault condition automatically halts the processor.
EDx
DI
EAx
EPC
PCI
Name
Setting an EDx bit enables the corresponding data breakpoint condition based on the size and placement
on the processor’s local data bus. Clearing all EDx bits disables data breakpoints.
EDLW
EDWL
EDWU Upper data word.
EDLL
EDLM
EDUM Upper middle data byte. Low-order byte of the high-order word.
EDUU
Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint comparators.
This can develop a trigger based on the occurrence of a data value other than the DBR contents.
Enable address bits. Setting an EA bit enables the corresponding address breakpoint. Clearing all three
bits disables the breakpoint.
EAI
EAR
EAL
Enable PC breakpoint. If set, this bit enables the PC breakpoint.
Breakpoint invert. If set, this bit allows execution outside a given region as defined by PBR and PBMR to
enable a trigger. If cleared, the PC breakpoint is defined within the region defined by PBR and PBMR.
Data longword. Entire processor’s local data bus.
Lower data word.
Lower lower data byte. Low-order byte of the low-order word.
Lower middle data byte. High-order byte of the low-order word.
Upper upper data byte. High-order byte of the high-order word.
Enable address breakpoint inverted. Breakpoint is based outside the range between ABLR and
ABHR.
Enable address breakpoint range. The breakpoint is based on the inclusive range defined by
ABLR and ABHR.
Enable address breakpoint low. The breakpoint is based on the address in the ABLR.
Table 5-14. TDR Field Descriptions (Continued)
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MCF5307 User’s Manual
Description