MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 147

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.5.2.1 Receive Packet Format
The basic receive packet, Figure 5-14, consists of 16 data bits and 1 status bit.
Table 5-15 describes receive BDM packet fields.
5.5.2.2 Transmit Packet Format
The basic transmit packet, Figure 5-15, consists of 16 data bits and 1 control bit.
Table 5-16 describes transmit BDM packet fields.
5.5.3 BDM Command Set
Table 5-17 summarizes the BDM command set. Subsequent paragraphs contain detailed
descriptions of each command. Issuing a BDM command when the processor is accessing
debug module registers using the WDEBUG instruction causes undefined behavior.
16
15–0 Data
Bits
16
15–0 Data
Bits
16
S
16
C
S
Name
C
Name
15
15
Control. This bit is reserved. Command and data transfers initiated by the development system
should clear C.
Contains the data to be sent from the development system to the debug module.
Status. Indicates the status of CPU-generated messages listed below. The not-ready response can
be ignored unless a memory-referencing cycle is in progress. Otherwise, the debug module can
accept a new serial transfer after 32 processor clock periods.
S
0
0
1
1
1
response message is always a single word, with the data field encoded as shown above.
Data. Contains the message to be sent from the debug module to the development system. The
Data
xxxx
0xFFFF
0x0000
0x0001
0xFFFF
Table 5-16. Transmit BDM Packet Field Description
Table 5-15. Receive BDM Packet Field Description
Freescale Semiconductor, Inc.
Message
Valid data transfer
Status OK
Not ready with response; come again
Error—Terminated bus cycle; data invalid
Illegal command
For More Information On This Product,
Figure 5-15. Transmit BDM Packet
Figure 5-14. Receive BDM Packet
Chapter 5. Debug Support
Go to: www.freescale.com
Data Field [15:0]
D[15:0]
Description
Description
Background Debug Mode (BDM)
5-19
0
0