MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 150

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Background Debug Mode (BDM)
The sequence is as follows:
5-22
• In cycle 1, the development system command is issued (
• In cycle 2, the development system supplies the high-order 16 address bits. The
• In cycle 3, the development system supplies the low-order 16 address bits. The
• At the completion of cycle 3, the debug module initiates a memory read operation.
COMMANDS TRANSMITTED TO THE DEBUG MODULE
RESPONSES FROM THE DEBUG MODULE
READ (LONG)
debug module responds with either the low-order results of the previous command
or a command complete status of the previous command, if no results are required.
debug module returns a not-ready response unless the received command is decoded
as unimplemented, which is indicated by the illegal command encoding. If this
occurs, the development system should retransmit the command.
debug module always returns a not-ready response.
Any serial transfers that begin during a memory access return a not-ready response.
???
RESULTS FROM PREVIOUS COMMAND
COMMAND CODE TRANSMITTED DURING THIS CYCLE
A not-ready response can be ignored except during a
memory-referencing cycle. Otherwise, the debug module can
accept a new serial transfer after 32 processor clock periods.
SEQUENCE TAKEN IF
ILLEGAL COMMAND
IS RECEIVED BY DEBUG MODULE
"NOT READY"
Figure 5-17. Command Sequence Diagram
MS ADDR
"ILLEGAL"
Freescale Semiconductor, Inc.
XXX
For More Information On This Product,
HIGH-ORDER 16 BITS OF MEMORY ADDRESS
Go to: www.freescale.com
DATA UNUSED FROM
THIS TRANSFER
"NOT READY"
"NOT READY"
MCF5307 User’s Manual
NEXT CMD
LS ADDR
LOW-ORDER 16 BITS OF MEMORY ADDRESS
NOTE:
LOCATION
MEMORY
READ
NONSERIAL-RELATED ACTIVITY
HIGH- AND LOW-ORDER
16 BITS OF RESULT
READ
ERROR OCCURS ON
SEQUENCE TAKEN IF
OPERATION HAS NOT
COMPLETED
SEQUENCE TAKEN IF BUS
MEMORY ACCESS
"NOT READY"
MS RESULT
XXX
XXX
XXXXX
BERR
XXX
in this example). The
"NOT READY"
COMMAND
NEXT CMD
LS RESULT
NEXT CMD
NEXT
CODE