MPC564CVR40 Freescale Semiconductor, MPC564CVR40 Datasheet - Page 1055

• Manufacturer Part Number: MPC564CVR40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CVR40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 25
IEEE 1149.1-Compliant Interface (JTAG)
The chip design includes user-accessible test logic that is compatible with the IEEE 1149.1-1994 Standard
Test Access Port and Boundary Scan Architecture. The implementation supports circuit-board test
strategies based on this standard. An overview of the pins requirement on JTAG is shown in
25.1
The MPC561/MPC563 provides a dedicated user-accessible test access port (TAP) that is compatible with
the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture in all but two areas listed
below. Problems associated with testing high density circuit boards have led to development of this
proposed standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test
Action Group (JTAG). The MPC561/MPC563 implementation supports circuit-board test strategies based
on this standard.
IEEE1149.1 Compatibility Exceptions:
Freescale Semiconductor
•
•
The MPC561/MPC563 enters JTAG mode by going through a standard device reset sequence with
the JCOMP signal asserted high during PORESET negation. Once JTAG has been entered, the
MPC561/MPC563 remains in JTAG mode until another reset sequence is applied to exit JTAG
mode, or the device is powered down.
The JTAG output port, TDO, is configured with a weak pull-up until reset negates or the driver is
disabled.
IEEE 1149.1 Test Access Port
JCOMP / RSTI
TDI
TCK
TMS
TDO
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 25-1. Pin Requirement on JTAG
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TRST
MPC561/MPC563
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bsc
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Figure
25-1.
25-1