MPC564CVR40 Freescale Semiconductor, MPC564CVR40 Datasheet - Page 330

IC MPU 32BIT W/CODE COMP 388PBGA

MPC564CVR40

Manufacturer Part Number
MPC564CVR40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564CVR40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC564CVR40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Clocks and Power Control
During the power down sequence PORESET needs to be asserted while VDD, NVDDL, and QVDDL are
at a voltage greater than or equal to 2.5 V. Below this voltage the power supply chip can be turned off.
If the turn-off voltage of the power supply chip is greater than 0.74 V for the 2.6-V supply and greater than
0.8 V for the 5-V supply, then the circuitry inside the MPC561/MPC563 will act as a load to the respective
supply and will discharge the supply line down to these values. Since the 2.6-V logic represents a larger
load to the supply chip, the 2.6-V supply line will decay faster than the 5-V supply line.
8-28
VFLASH (5 V)
1
2
3
4
5
VDDA, VRH
IRAMSTBY
VDD, NVVL,
QVDDL
VDDH ≥ QVDDL - 0.5 V
VDDA can lag VDDH, and VDDSYN can lag QVDDL, but both must be at a valid level before resets are negated.
If keep-alive functions are NOT used, then when system power is on: KAPWR = QVDDL ± 0.1 V; KAPWR ≤ 2.7 V
If keep-alive functions ARE used, then KAPWR = QVDDL = NVDDL = 2.6 V ± 0.1 V when system power is on
KAPWR = 2.6 V ± 0.1 V when system power is off. IRAMSTBY should be powered prior to the other supplies. If
IRAMSTBY is powered at the same time as the other supplies, it should be allowed to stabilize before PORESET
is negated. Normal system power is defined as QVDDL = VDD = VDDF = VDDSYN = KAPWR = 2.6 ± 0.1 V and
VDDA = VDDH = VFLASH = 5.0 ± 0.25 V. Flash programming requirements are the same as normal system
power. VFLASH should always be 5.0 ± 0.25 V. Note: Flash is not implemented on the MPC561.
Do not hold the 2.6-V supplies at ground while VDDH/VDDA is ramping to 5 V.
If 5 V is applied before the 2.6-V supply, all 5-V outputs will be in indeterminate states until the 2.6-V supply
reaches a level that allows reset to be distributed throughout the device If 5 V is applied before the 2.6-V supply,
all 5-V outputs will be in indeterminate states until the 2.6-V supply reaches a level that allows reset to be
distributed throughout the device
PORESET
VDDSYN
HRESET
KAPWR
VDDH
Figure 8-14. No Standby, No KAPWR, All System Power-On/Off
MPC561/MPC563 Reference Manual, Rev. 1.2
Power On
See Note 1.
Operating
See Note 2.
Power Off
Freescale Semiconductor

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