MPC564CVR40 Freescale Semiconductor, MPC564CVR40 Datasheet - Page 349

IC MPU 32BIT W/CODE COMP 388PBGA

MPC564CVR40

Manufacturer Part Number
MPC564CVR40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564CVR40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC564CVR40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
9.5.2
During the data transfer phase, the data is transferred from master to slave (in write cycles) or from slave
to master (on read cycles).
During a write cycle, the master drives the data as soon as it can, but never earlier than the cycle following
the address transfer phase. The master has to take into consideration the “one dead clock cycle” switching
between drivers to avoid electrical contentions. The master can stop driving the data bus as soon as it
samples the TA line asserted on the rising edge of the CLKOUT.
During a read cycle, the master accepts the data bus contents as valid at the rising edge of the CLKOUT
in which the TA signal is sampled/asserted.
9.5.2.1
The basic read cycle begins with bus arbitration, followed by the address transfer, then the data transfer.
The handshakes illustrated in the following flow and timing figures
Figure
Freescale Semiconductor
9-6) are applicable to the fixed transaction protocol.
Single Beat Transfer
Single Beat Read Flow
4. Assert transfer start (TS)
3. Assert bus busy (BB) if no other master is driving bus
5. Drive address and attributes
2. Receive bus grant (BG) from arbiter
1. Request bus (BR)
Figure 9-4. Basic Flow Diagram of a Single Beat Read Cycle
Master
MPC561/MPC563 Reference Manual, Rev. 1.2
1. Receive address
2. Return data
3. Assert transfer acknowledge (TA)
(Figure
Slave
9-4,
Figure
External Bus Interface
9-5, and
9-9

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