MPC564CVR40 Freescale Semiconductor, MPC564CVR40 Datasheet - Page 682

• Manufacturer Part Number: MPC564CVR40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CVR40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Queued Serial Multi-Channel Module
15-64
•
•
•
•
•
•
•
restart transmitting from the top of the queue (SCTQ0). After each wrap, QTWE is cleared by
hardware.
— Transmissions of more than 16 data frames must be performed in multiples of 16 (QTSZ =
Interrupt generation when the top half (SCTQ[0:7]) of the queue has been emptied (QTHE) and the
bottom half (SCTQ[8:15]) of the queue has been emptied (QBHE). This may allow for
uninterrupted and continuous transmits by indicating to the CPU that it can begin refilling the
queue portion that is now emptied.
— The QTHE bit is set by hardware when the top half is empty or the transmission has completed.
— The QBHE bit is set by hardware when the bottom half is empty or the transmission has
— In order to implement the transmit queue, QTE must be set (QSCI1CR), TE must be set
Enable and disable options for the interrupts QTHE and QBHE as controlled by QTHEI and
QBHEI respectfully.
Programmable 4-bit register queue transmit size (QTSZ) for configuring the queue to any size up
to 16 transfers at a time. This value may be rewritten after transmission has started to allow for the
wrap feature.
4-bit status register to indicate the number of data transfers pending (QPEND). This register counts
down to all 0’s where the next count rolls over to all 1’s. This counter is writable in test mode;
otherwise it is read-only.
4-bit counter (QTPNT) is used as a pointer to indicate the next data frame within the transmit queue
to be loaded into the SC1DR. This counter is writable in test mode; otherwise it is read-only.
A transmit complete (TC) bit re-defined when the queue is enabled (QTE = 1) to indicate when the
entire queue (including when wrapped) is finished transmitting. This is indicated when QPEND =
1111 and the shifter has completed shifting data out. TC is cleared when the SCxSR is read with
TC = 1 followed by a write to SCTQ[0:15]. If the queue is disabled (QTE = 0), the TC bit operates
as originally designed.
When the transmit queue is enabled (QTE = 1), writes to the transmit data register (SC1DR) have
no effect.
0b1111) except for the last set of transmissions. For any single non-continuous transmissions
of 16 or less or the last transmit set composed of 16 or fewer data frames, programming of
QTSZ to the corresponding value of 16 or less where QTWE = 0 is allowed.
The QTHE bit is cleared when the QSCI1SR is read with QTHE set, followed by a write of
QTHE to zero.
completed. The QBHE bit is cleared when the QSCI1SR is read with QBHE set, followed by
a write of QBHE to zero.
(SCC1R1), QTHE must be cleared (QSCI1SR), and TDRE must be set (SC1SR).
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor