MPC564CVR40 Freescale Semiconductor, MPC564CVR40 Datasheet - Page 598

• Manufacturer Part Number: MPC564CVR40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CVR40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

QADC64E Enhanced Mode Operation
The next two situations consider trigger events that occur for the lower priority queue 2, while queue 1 is
actively being serviced.
Situation S4
is saved, and as soon as queue 1 is finished, queue 2 servicing begins.
Situation S5
busy, the trigger overrun error bit is set, but queue 1 execution is not disturbed. Situation S5 also shows
that the effect of queue 2 trigger events during queue 1 execution is the same when the pause feature is in
use in either queue.
14-56
Q1
Q2
QS
Q1
Q2
QS
(Figure
(Figure
0000
IDLE
Q1:
IDLE
T1
0000
14-29) shows that when multiple queue 2 trigger events are detected while queue 1 is
14-28) shows that a queue 2 trigger event that is recognized while queue 1 is active
C1
ACTIVE
IDLE
TOR1
T1
1000
IDLE
C2
Q1:
PF1
T1
0100
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 14-27. CCW Priority Situation 3
C1
Figure 14-28. CCW Priority Situation 4
Q2:
1000
T2
C2
ACTIVE
PAUSE
Q2:
C1
ACTIVE
TOR2
T2
T2
0110
TRIGGERED
C3
C2
1011
PF2
C4
0101
CF1
T1
C1
C3
ACTIVE
TOR1
T1
1001
PAUSE
C2
ACTIVE
C4
0010
CF1
C3
0001
C4
CF2
T2
IDLE
C3
ACTIVE
TOR2
T2
0010
IDLE
C4
CF2
IDLE
0000
Freescale Semiconductor
IDLE
0000
QADC S3
QADC S4