MPC564CVR40 Freescale Semiconductor, MPC564CVR40 Datasheet - Page 620

• Manufacturer Part Number: MPC564CVR40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CVR40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Queued Serial Multi-Channel Module
15.2
Standard SPI features are listed below, followed by a list of the additional features offered on the QSPI:
QSPI-enhanced features are as follows:
15-2
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IMB3*
Full-duplex, three-wire synchronous transfers
Half-duplex, two-wire synchronous transfers
Master or slave operation on the SPI bus
Programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Master-master mode fault flag
Easily interfaces to simple expansion parts (A/D converters, EEPROMS, display drivers, etc.)
Programmable Queue — up to 32 preprogrammed transfers
Programmable Peripheral Chip-Selects — four pins select up to 16 SPI chips
Wraparound Transfer Mode — for autoscanning of serial A/D (or other) peripherals, with no CPU
overhead
Programmable Transfer Length — from 8–16 bits inclusive
Key Features
Note: SBIU bus and interface to IMB3 are each 16 bits wide.
Receive and Transmit Queue
MPC561/MPC563 Reference Manual, Rev. 1.2
QSPI QUEUE RAM
Figure 15-1. QSMCM Block Diagram
QSPI
DSCI
DSCI
SBIU
SCI2
SCI1
2
7
2
Freescale Semiconductor
SCK/QGPIO6
PCS1/QGPIO1
PCS3/QGPIO3
RXD1/QGPI1
TXD2/QGPO2
MISO/QGPIO4
MOSI/QGPIO5
PCS0/SS/QGPIO0
PCS2/QGPIO2
TXD1/QGPO1
RXD2/QGPI2