MPC564CVR40 Freescale Semiconductor, MPC564CVR40 Datasheet - Page 696

IC MPU 32BIT W/CODE COMP 388PBGA

MPC564CVR40

Manufacturer Part Number
MPC564CVR40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564CVR40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC564CVR40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
CAN 2.0B Controller Module
16.2
Each TouCAN module interface to the external CAN bus consists of two signals: CNTX0 which transmits
serial data, and CNRX0 which receives serial data.
16-2
— Zero to eight bytes data length
— Programmable bit rate up to one Mbit/sec
16 Rx/Tx message buffers of 0-8 bytes data length
Content-related addressing
No read/write semaphores required
Three programmable mask registers: global (for message buffers 0 through 13), special for
message buffer 14, and special for message buffer 15
Programmable transmit-first scheme: lowest ID or lowest buffer number
“Time stamp”, based on 16-bit free-running timer
Global network time, synchronized by a specific message
Programmable I/O modes
Maskable interrupts
Independent of the transmission medium (external transceiver is assumed)
Open network architecture
Multimaster concept
High immunity to EMI
Short latency time for high-priority messages
Low power sleep mode with programmable wakeup on bus activity
Outputs have open drain drivers
Support for SAE J1939 and SAE J2284
Support for DeviceNet™ and Smart Distributed System
External Signals
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor

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