MPC564CVR40 Freescale Semiconductor, MPC564CVR40 Datasheet - Page 955

IC MPU 32BIT W/CODE COMP 388PBGA

MPC564CVR40

Manufacturer Part Number
MPC564CVR40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564CVR40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC564CVR40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
23.6.2
Note: These registers are unaffected by reset.
23.6.3
The ECR indicates the cause of entry into debug mode. All bits are set by the hardware and cleared when
the register is read when debug mode is disabled, or if the processor is in debug mode. Attempts to write
to this register are ignored. When the hardware sets a bit in this register, debug mode is entered only if
debug mode is enabled and the corresponding mask bit in the DER is set.
All bits are cleared to zero following reset.
Freescale Semiconductor
Reset
Reset
MSR[PR]
0:31
Bits
Field
Field
Addr
0
0
0
1
Comparator A–D Value Registers (CMPA–CMPD)
Exception Cause Register (ECR)
MSB
16
0
Mnemonic
Debug Mode
17
Table 23-16. Development Support Registers Write Access Protection
1
CMPA-D
Enable
Figure 23-15. Comparator A–D Value Register (CMPA–CMPD)
X
0
1
1
18
2
19
3
Table 23-17. CMPA-CMPD Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
In Debug Mode
Address bits to be compared
20
4
X
X
0
1
21
5
Write is performed.
Write to ECR is ignored.
Writing to DPDR is ignored.
Write is not performed.
Writing to DPDR is ignored.
Write is performed.
Write to ECR is ignored.
Write is not performed.
Program exception is generated.
22
6
SPR144–SPR147
Unaffected
Unaffected
23
CMPA-D
CMPAD
7
24
8
Description
25
9
10
26
Result
11
27
12
28
13
29
Development Support
14
30
LSB
15
31
23-41

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